Assembler Language Reference

Extended Mnemonics of 32-bit Fixed-Point Rotate and Shift Instructions

A set of extended mnemonics are provided for extract, insert, rotate, shift, clear, and clear left and shift left operations. This article discusses the following:

Alternative Input Format

The alternative input format is applied to the following POWER family and PowerPC instructions.

POWER family	PowerPC
rlimi[.]	rlwimi[.]
rlinm[.]	rlwinm[.]
rlnm[.]	rlwnm[.]
rlmi[.]	Not applicable

Five operands are normally required for these instructions. These operands are:

RA, RS, SH, MB, ME

MB indicates the first bit with a value of 1 in the mask, and ME indicates the last bit with a value of 1 in the mask. The assembler supports the following operand format.

RA, RS, SH, BM

BM is the mask itself. The assembler generates the MB and ME operands from the BM operand for the instructions. The assembler checks the BM operand first. If an invalid BM is entered, error 78 is reported.

A valid mask is defined as a single series (one or more) of bits with a value of 1 surrounded by zero or more bits with a value of z0. A mask of all bits with a value of 0 may not be specified.

Examples of Valid 32-bit Masks

The following shows examples of valid 32-bit masks.

                           0             15              31
                           |              |               |
-----------------------------------------------------------
MB = 0       ME = 31       11111111111111111111111111111111
MB = 0       ME = 0        10000000000000000000000000000000
MB = 0       ME = 22       11111111111111111111110000000000
MB = 12      ME = 25       00000000000111111111111110000000
-----------------------------------------------------------
MB = 22      ME = 31       00000000000000000000011111111111
MB = 29      ME = 6        11111110000000000000000000000111

Examples of 32-bit Masks That Are Not Valid

The following shows examples of 32-bit masks that are not valid.

0              15             31
|               |              |
00000000000000000000000000000000
01010101010101010101010101010101
00000000000011110000011000000000
11111100000111111111111111000000

32-bit Rotate and Shift Extended Mnemonics for POWER family and PowerPC

The extended mnemonics for the rotate and shift instructions are in the POWER family and PowerPC intersection area (com assembly mode). A set of rotate and shift extended mnemonics provide for the following operations:

Extract	Selects a field of n bits starting at bit position b in the source register. This field is right- or left-justified in the target register. All other bits of the target register are cleared to 0.
Insert	Selects a left- or right-justified field of n bits in the source register. This field is inserted starting at bit position b of the target register. Other bits of the target register are unchanged. No extended mnemonic is provided for insertion of a left-justified field when operating on doublewords, since such an insertion requires more than one instruction.
Rotate	Rotates the contents of a register right or left n bits without masking.
Shift	Shifts the contents of a register right or left n bits. Vacated bits are cleared to 0 (logical shift).
Clear	Clears the leftmost or rightmost n bits of a register to 0.
Clear left and shift left	Clears the leftmost b bits of a register, then shifts the register by n bits. This operation can be used to scale a known nonnegative array index by the width of an element.

The rotate and shift extended mnemonics are shown in the following table. The N operand specifies the number of bits to be extracted, inserted, rotated, or shifted. Because expressions are introduced when the extended mnemonics are mapped to the base mnemonics, certain restrictions are imposed to prevent the result of the expression from causing an overflow in the SH, MB, or ME operand.

To maintain compatibility with previous versions of AIX, n is not restricted to a value of 0. If n is 0, the assembler treats 32-n as a value of 0.

Table 21. 32-bit Rotate and Shift Extended Mnemonics for PowerPC
Operation	Extended Mnemonic	Equivalent to	Restrictions
Extract and left justify immediate	extlwi RA, RS, n, b	rlwinm RA, RS, b, 0, n-1	32 > n > 0
Extract and right justify immediate	extrwi RA, RS, n, b	rlwinm RA, RS, b+n, 32-n, 31	32 > n > 0 & b+n =< 32
Insert from left immediate	inslwi RA, RS, n, b	rlwinm RA, RS, 32-b, b, (b+n)-1	b+n <=32 & 32>n > 0 & 32 > b >= 0
Insert from right immediate	insrwi RA, RS, n, b	rlwinm RA, RS, 32-(b+n), b, (b+n)-1	b+n <= 32 & 32>n > 0
Rotate left immediate	rotlwi RA, RS, n	rlwinm RA, RS, n, 0, 31	32 > n >= 0
Rotate right immediate	rotrwi RA, RS, n	rlwinm RA, RS, 32-n, 0, 31	32 > n >= 0
Rotate left	rotlw RA, RS, b	rlwinm RA, RS, RB, 0, 31	None
Shift left immediate	slwi RA, RS, n	rlwinm RA, RS, n, 0, 31-n	32 > n >= 0
Shift right immediate	srwi RA, RS, n	rlwinm RA, RS, 32-n, n, 31	32 > n >= 0
Clear left immediate	clrlwi RA, RS, n	rlwinm RA, RS, 0, n, 31	32 > n >= 0
Clear right immediate	clrrwi RA, RS, n	rlwinm RA, RS, 0, 0, 31-n	32 > n >= 0
Clear left and shift left immediate	clrslwi RA, RS, b, n	rlwinm RA, RS, b-n, 31-n	b-n >= 0 & 32 > n >= 0 & 32 > b>= 0

Notes:

In POWER family, the mnemonic slwi[.] is sli[.]. The mnemonic srwi[.] is sri[.].
All of these extended mnemonics can be coded with a final . (period) to cause the Rc bit to be set in the underlying instruction.

Examples

To extract the sign bit (bit 31) of register RY and place the result right-justified into register RX:
```
extrwi   RX, RY, 1, 0
```
This is equivalent to:
```
rlwinm   RX, RY, 1, 31, 31
```
To insert the bit extracted in Example 1 into the sign bit (bit 31) of register RX:
```
insrwi   RZ, RX, 1, 0
```
This is equivalent to:
```
rlwimi   RZ, RX, 31, 0, 0
```
To shift the contents of register RX left 8 bits and clear the high-order 32 bits:
```
slwi   RX, RX, 8
```
This is equivalent to:
```
rlwinm   RX, RX, 8, 0, 23
```
To clear the high-order 16 bits of the low-order 32 bits of register RY and place the result in register RX, and clear the high-order 32 bits of register RX:
```
clrlwi   RX, RY, 16
```
This is equivalent to:
```
rlwinm   RX, RY, 0, 16, 31
```

Related Information

Extended Instruction Mnemonics.

Extended Mnemonics of Branch Instructions.

Extended Mnemonics of Condition Register Logical Instructions.

Extended Mnemonics of Fixed-Point Arithmetic Instructions.

Extended Mnemonics of Fixed-Point Compare Instructions.

Extended Mnemonics of Fixed-Point Load Instructions.

Extended Mnemonics of Fixed-Point Logical Instructions.

Extended Mnemonics of Fixed-Point Trap Instructions.

Extended Mnemonics of Moving from or to Special-Purpose Registers.

addic or ai (Add Immediate Carrying) Instruction, addic. or ai. (Add Immediate Carrying and Record) Instruction, bc (Branch Conditional) Instruction, bclr or bcr (Branch Conditional Link Register) Instruction, bcctr or bcc (Branch Conditional to Count Register) Instruction, addi (Add Immediate) or cal (Compute Address Lower) Instruction, addis or cau (Add Immediate Shifted) Instruction, cmpi (Compare Immediate) Instruction, cmp (Compare) Instruction, cmpli (Compare Logical Immediate) Instruction, cmpl (Compare Logical) Instruction, creqv (Condition Register Equivalent) Instruction, cror (Condition Register OR) Instruction, crnor (Condition Register NOR) Instruction, crxor (Condition Register XOR) Instruction, mfspr (Move from Special-Purpose Register) Instruction, mtspr (Move to Special-Purpose Register) Instruction, nor (NOR) Instruction, or (OR) Instruction, rlwinm or rlinm (Rotate Left Word Immediate Then AND with Mask) Instruction, tw or t (Trap Word) Instruction, twi or ti (Trap Word Immediate) Instruction.