Assembler Language Reference

rlwinm or rlinm (Rotate Left Word Immediate Then AND with Mask) Instruction

Purpose

Logically ANDs a generated mask with the result of rotating left by a specified number of bits in the contents of a general-purpose register.

Syntax

Bits	Value
0-5	21
6-10	RS
11-15	RA
16-20	SH
21-25	MB
26-30	ME
31	Rc

PowerPC
rlwinm	RA, RS, SH, MB, ME
rlwinm.	RA, RS, SH, MB, ME
rlwinm	RA, RS, SH, BM
rlwinm.	RA, RS, SH, BM

POWER family
rlinm	RA, RS, SH, MB, ME
rlinm.	RA, RS, SH, MB, ME
rlinm	RA, RS, SH, BM
rlinm.	RA, RS, SH, BM

See Extended Mnemonics of Fixed-Point Rotate and Shift Instructions for more information.

Description

The rlwinm and rlinm instructions rotate left the contents of the source general-purpose register (GPR) RS by the number of bits specified by the SH parameter, logically AND the rotated data with a 32-bit generated mask defined by the values in Mask Begin (MB) and Mask End (ME), and store the result in GPR RA.

Consider the following when using the rlwinm and rlinm instructions:

If the MB value is less than the ME value + 1, then the mask bits between and including the starting point and the end point are set to ones. All other bits are set to zeros.

If the MB value is the same as the ME value + 1, then all 32 mask bits are set to ones.

If the MB value is greater than the ME value + 1, then all of the mask bits between and including the ME value +1 and the MB value -1 are set to zeros. All other bits are set to ones.

The BM parameter can also be used to specify the mask for these instructions. The assembler will generate the MB and ME parameters from the BM value.

The rlwinm and rlinm instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
rlwinm	None	None	0	None
rlwinm.	None	None	1	LT,GT,EQ,SO
rlinm	None	None	0	None
rlinm.	None	None	1	LT,GT,EQ,SO

The syntax forms of the rlwinm and rlinm instructions never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instructions affect the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA	Specifies target general-purpose register where result of operation is stored.
RS	Specifies source general-purpose register for operation.
SH	Specifies shift value for operation.
MB	Specifies begin value of mask for operation.
ME	Specifies end value of mask for operation.
BM	Specifies value of 32-bit mask.

Examples

The following code rotates the contents of GPR 4 to the left by 2 bits and logically ANDs the result with a mask of 29 ones:

# Assume GPR 4 contains 0x9000 3000.
# Assume GPR 6 contains 0xFFFF FFFF.
rlwinm 6,4,2,0,0x1D
# GPR 6 now contains 0x4000 C000.
# Under the same conditions
# rlwinm 6,4,2,0xFFFFFFFC
# will produce the same result.

The following code rotates the contents of GPR 4 to the left by 2 bits, logically ANDs the result with a mask of 29 ones, and sets Condition Register Field 0 to reflect the result of the operation:

# Assume GPR 4 contains 0xB004 3000.
# Assume GPR 6 contains 0xFFFF FFFF.
rlwinm. 6,4,2,0,0x1D
# GPR 6 now contains 0xC010 C000.
# CRF 0 now contains 0x8.
# Under the same conditions
# rlwinm. 6,4,2,0xFFFFFFFC
# will produce the same result.

Related Information

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .