Copies the contents of a special-purpose register into a general-purpose register.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | RT |
| 11-20 | spr |
| 21-30 | 339 |
| 31 | Rc |
| mfspr | RT, SPR |
Note: The special-purpose register is a split field.
See Extended Mnemonics of Moving from or to Special-Purpose Registers for more information.
The mfspr instruction copies the contents of the special-purpose register SPR into target general-purpose register (GPR) RT.
The special-purpose register identifier SPR can have any of the values specified in the following table. The order of the two 5-bit halves of the SPR number is reversed.
| SPR Values | |||
| Decimal | spr5:9 spr0:4 | Register Name | Privileged |
| 1 | 00000 00001 | XER | No |
| 8 | 00000 01000 | LR | No |
| 9 | 00000 01001 | CTR | No |
| 18 | 00000 10010 | DSISR | Yes |
| 19 | 00000 10011 | DAR | Yes |
| 22 | 00000 10110 | DEC2 | Yes |
| 25 | 00000 11001 | SDR1 | Yes |
| 26 | 00000 11010 | SRR0 | Yes |
| 27 | 00000 11011 | SRR1 | Yes |
| 272 | 01000 10000 | SPRG0 | Yes |
| 273 | 01000 10001 | SPRG1 | Yes |
| 274 | 01000 10010 | SPRG2 | Yes |
| 275 | 01000 10011 | SPRG3 | Yes |
| 282 | 01000 11010 | EAR | Yes |
| 284 | 01000 11100 | TBL | Yes |
| 285 | 01000 11101 | TBU | Yes |
| 528 | 10000 10000 | IBAT0U | Yes |
| 529 | 10000 10001 | IBAT0L | Yes |
| 530 | 10000 10010 | IBAT1U | Yes |
| 531 | 10000 10011 | IBAT1L | Yes |
| 532 | 10000 10100 | IBAT2U | Yes |
| 533 | 10000 10101 | IBAT2L | Yes |
| 534 | 10000 10110 | IBAT3U | Yes |
| 535 | 10000 10111 | IBAT3L | Yes |
| 536 | 10000 11000 | DBAT0U | Yes |
| 537 | 10000 11001 | DBAT0L | Yes |
| 538 | 10000 11010 | DBAT1U | Yes |
| 539 | 10000 11011 | DBAT1L | Yes |
| 540 | 10000 11100 | DBAT2U | Yes |
| 541 | 10000 11101 | DBAT2L | Yes |
| 542 | 10000 11110 | DBAT3U | Yes |
| 543 | 10000 11111 | DBAT3L | Yes |
| 0 | 00000 00000 | MQ1 | No |
| 4 | 00000 00100 | RTCU1 | No |
| 5 | 00000 00101 | RTCL1 | No |
| 6 | 00000 00110 | DEC2 | No |
1Supported only in the POWER family architecture.
2In the PowerPC architecture moving from the DEC register is privileged and the SPR value is 22. In the POWER family architecture moving from the DEC register is not privileged and the SPR value is 6. For more information, see Fixed-Point Move to or from Special-Purpose Registers Instructions .
If the SPR field contains any value other than those listed in the SPR Values table, the instruction form is invalid.
The mfspr instruction has one syntax form and does not affect the Fixed-Point Exception Register or Condition Register Field 0.
| RT | Specifies target general-purpose register where result of operation is stored. |
| SPR | Specifies source special-purpose register for operation. |
The following code copies the contents of the Fixed-Point Exception Register into GPR 6:
mfspr 6,1 # GPR 6 now contains the bit settings of the Fixed # Point Exception Register.
Fixed-Point Move to or from Special-Purpose Registers Instructions .