Invalidates a block containing the byte addressed in the instruction cache, causing subsequent references to retrieve the block from main memory.
Note: The icbi instruction is supported only in the PowerPC architecture.
The icbi instruction invalidates a block containing the byte addressed in the instruction cache. If RA is not 0, the icbi instruction calculates an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB.
Consider the following when using the icbi instruction:
The icbi instruction has one syntax form and does not affect Condition Register Field 0 or the Fixed-Point Exception Register.
|RA||Specifies source general-purpose register for the EA calculation.|
|RB||Specifies source general-purpose register for the EA calculation.|
The following code ensures that modified instructions are available for execution:
# Assume GPR 3 contains a modified instruction. # Assume GPR 4 contains the address of the memory location # where the modified instruction will be stored. stw 3,0(4) # Store the modified instruction. dcbf 0,4 # Copy the modified instruction to # main memory. sync # Ensure update is in main memory. icbi 0,4 # Invalidate block with old instruction. isync # Discard prefetched instructions. b newcode # Go execute the new code.
The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.
Processing and Storage