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AIX Version 4.3 Assembler Language Reference

clcs (Cache Line Compute Size) Instruction


Places a specified cache line size in a general-purpose register.

Note: The clcs instruction is supported only in the POWER architecture.


clcs RT,RA


The clcs instruction places the cache line size specified by RA into the target general-purpose register (GPR) RT. The value of RA determines the cache line size returned in GPR RT.

Value of RA Cache Line Size Returned in RT
00xxx Undefined
010xx Undefined
01100 Instruction Cache Line Size
01101 Data Cache Line Size
01110 Minimum Cache Line Size
01111 Maximum Cache Line Size
1xxxx Undefined
Note: The value in GPR RT must lie between 64 and 4096, inclusive, or results will be undefined.

The clcs instruction has only one syntax form and does not affect the Fixed-Point Exception Register. If the Record (Rc) bit is set to 1, the Condition Register Field 0 is undefined.


RT Specifies target general-purpose register where result of operation is stored.
RA Specifies cache line size requested.


The following code loads the maximum cache line size into GPR 4:

# Assume that 0xf is the cache 
line size requested
    clcs 4,0xf
# GPR 4 now contains the maximum Cache Line size. 

Related Information

The clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.

Processing and Storage: Overview.

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