Refetches any instructions that might have been fetched prior to this instruction.
The isync and ics instructions cause the processor to refetch any instructions that might have been fetched prior to the isync or ics instruction.
The PowerPC instruction isync causes the processor to wait for all previous instructions to complete. Then any instructions already fetched are discarded and instruction processing continues in the environment established by the previous instructions.
The POWER instruction ics causes the processor to wait for any previous dcs instructions to complete. Then any instructions already fetched are discarded and instruction processing continues under the conditions established by the content of the Machine State Register.
The isync and ics instructions have one syntax form and do not affect Condition Register Field 0 or the Fixed-Point Exception Register.
The following code refetches instructions before continuing:
# Assume GPR 5 holds name. # Assume GPR 3 holds 0x0. name: dcbf 3,5 isync
The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Line Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.
Processing and Storage
Functional Differences for POWER and PowerPC Instructions.