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AIX Version 4.3 Assembler Language Reference

dclst (Data Cache Line Store) Instruction


Stores a line of modified data in the data cache into main memory.

Note: The dclst instruction is supported only in the POWER architecture.


dclst RA,RB


The dclst instruction adds the contents of general-purpose register (GPR) RA to the contents of GPR RB. It then stores the sum in RA as the effective address (EA) if RA is not 0 and the instruction does not cause a Data Storage interrupt.

If RA is 0, the effective address (EA) is the sum of the contents of GPR RB and 0.

Consider the following when using the dclst instruction:

The dclst instruction has one syntax form and does not effect the Fixed-Point Exception register. If the Record (Rc) bit is set to 1, Condition Register Field 0 is undefined.


RA Specifies the source and target general-purpose register where result of operation is stored.
RB Specifies the source general-purpose register for EA calculation.


The following code stores the sum of the contents of GPR 4 and GPR 6 in GPR 6 as the effective address:

# Assume that GPR 4 contains 0x0000 3000.
# Assume that GPR 6 is the target register and that it
# contains 0x0000 0000.
dclst 6,4
# GPR 6 now contains 0x0000 3000.

Related Information

The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.

Processing and Storage

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