dclst (Data Cache Line Store) Instruction

Purpose

Stores a line of modified data in the data cache into main memory.

Note: The dclst instruction is supported only in the POWER architecture.

Syntax

Description

The dclst instruction adds the contents of general-purpose register (GPR) RA to the contents of GPR RB. It then stores the sum in RA as the effective address (EA) if RA is not 0 and the instruction does not cause a Data Storage interrupt.

If RA is 0, the effective address (EA) is the sum of the contents of GPR RB and 0.

Consider the following when using the dclst instruction:

• If the line containing the byte addressed by the EA is in the data cache and has been modified, the dclst instruction writes the line to main memory.
• If data address translation is enabled (that is, the Machine State Register (MSR) Data Relocate (DR) bit is 1) and the virtual address has no translation, a Data Storage interrupt occurs with bit 1 of the Data Storage Interrupt Segment Register set to 1.
• If data address translation is enabled (MSR DR bit is 1), the virtual address translates to an unusable real address, the line exists in the data cache, and a Machine Check interrupt occurs.
• If data address translation is disabled (MSR DR bit is 0) the address specifies an unusable real address, the line exists in the data cache, and a Machine Check interrupt occurs.
• If the EA specifies an I/O address, the instruction is treated as a no-op, but the effective address is placed into GPR RA.
• Address translation treats the dclst instruction as a load to the byte addressed, ignoring protection and data locking. If this instruction causes a Translation Look-Aside Buffer (TLB) miss, the reference bit is set.

The dclst instruction has one syntax form and does not effect the Fixed-Point Exception register. If the Record (Rc) bit is set to 1, Condition Register Field 0 is undefined.

Parameters

Examples

The following code stores the sum of the contents of GPR 4 and GPR 6 in GPR 6 as the effective address:

# Assume that GPR 4 contains 0x0000 3000.
# Assume that GPR 6 is the target register and that it
# contains 0x0000 0000.
dclst 6,4
# GPR 6 now contains 0x0000 3000.

Related Information

The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.

Processing and Storage