dcbst (Data Cache Block Store) Instruction

Purpose

Allows a program to copy the contents of a modified block to main memory.

Note: The dcbst instruction is supported only in the PowerPC architecture.

Syntax

Description

The dcbst instruction causes any modified copy of the block to be copied to main memory. If RA is not 0, the dcbst instruction computes an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. Otherwise, the EA is the contents of RB. If the cache block containing the addressed byte is in the data cache and is modified, the block is copied to main memory.

The dcbst instruction may be used to ensure that the copy of a location in main memory contains the most recent updates. This may be important when sharing memory with an I/O device that does not participate in the coherence protocol. In addition, the dcbst instruction can ensure that updates are immediately copied to a graphics frame buffer.

Treat the dcbst instruction as a load from the addressed byte with respect to address translation and protection.

The dcbst instruction has one syntax form and does not effect the Fixed-Point Exception register.

Parameters

Examples

1. The following code shares memory with an I/O device that does not participate in the coherence protocol:

   # Assume that location A is memory that is shared with the
   # I/O device.
   # Assume that GPR 2 contains a control value indicating that
   # and I/O operation should start.
   # Assume that GPR 3 contains the new value to be placed in
   # location A.
   # Assume that GPR 4 contains the address of location A.
   # Assume that GPR 5 contains the address of a control register
   # in the I/O device.
   st      3,0,4           # Update location A.
   dcbst   0,4             # Copy new content of location A and
                           # other bytes in cache block to main
                           # memory.
   sync                    # Ensure the dcbst instruction has 
                           # completed.
   st      2,0,5           # Signal I/O device that location A has
                           # been update.

2. The following code copies to a graphics frame buffer, ensuring that new values are displayed without delay:

   # Assume that target memory is a graphics frame buffer.
   # Assume that GPR 2, 3, and 4 contain new values to be displayed.
   # Assume that GPR 5 contains the address minus 4 of where the
   # first value is to be stored.
   # Assume that the 3 target locations are known to be in a single
   # cache block.
   addi    6,5,4           # Compute address of first memory
                           # location.
   stwu    2,4(5)          # Store value and update address ptr.
   stwu    3,4(5)          # Store value and update address ptr.
   stwu    4,4(5)          # Store value and update address ptr.
   dcbst   0,6             # Copy new content of cache block to
                           # frame buffer. New values are displayed.

Related Information

The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.

Processing and Storage: Overview.