Invalidates a line containing the byte addressed in either the data or instruction cache, causing subsequent references to retrieve the line again from main memory.
Note: The cli instruction is supported only in the POWER architecture.
The cli instruction invalidates a line containing the byte addressed in either the data or instruction cache. If RA is not 0, the cli instruction calculates an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. If RA is not GPR 0 or the instruction does not cause a Data Storage interrupt, the result of the calculation is placed back into GPR RA.
Consider the following when using the cli instruction:
The cli instruction has only one syntax form and does not effect the Fixed-Point Exception Register. If the Record (Rc) bit is set to 1, the Condition Register Field 0 is undefined.
|RA||Specifies the source general-purpose register for EA calculation and possibly the target general-purpose register (when RA is not GPR 0) for operation.|
|RB||Specifies the source general-purpose register for EA calculation.|
The cli instruction is privileged.
The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.
Processing and Storage: Overview.