The PowerPC instruction, dcbz, sets all bytes of a cache block to 0.
The POWER instruction, dclz,sets all bytes of a cache line to 0.
| PowerPC | |
|---|---|
| dcbz | RA,RB |
| POWER | |
|---|---|
| dclz | RA,RB |
The dcbz and dclz instructions work with data cache blocks and data cache lines respectively. If RA is not 0, the dcbz and dclz instructions compute an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. If GPR RA is 0, the EA is the contents of GPR RB.
If the cache block or line containing the addressed byte is in the data cache, all bytes in the block or line are set to 0. Otherwise, the block or line is established in the data cache without reference to storage and all bytes of the block or line are set to 0.
For the POWER instruction dclz, if GPR RA is not 0, the EA replaces the content of GPR RA.
The dcbz and dclz instructions are treated as a store to the addressed cache block or line with respect to protection.
The dcbz and dclz instructions have one syntax form and do not effect the Fixed-Point Exception Register. If bit 31 is set to 1, the instruction form is invalid.
| PowerPC | |
|---|---|
| RA | Specifies the source register for EA computation. |
| RB | Specifies the source register for EA computation. |
| POWER | |
|---|---|
| RA | Specifies the source register for EA computation and the target register for EA update. |
| RB | Specifies the source register for EA computation. |
The dclz instruction is privileged.
The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.