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AIX Version 4.3 Assembler Language Reference

## div (Divide) Instruction

### Purpose

Divides the contents of a general-purpose register concatenated with the MQ Register by the contents of a general-purpose register and stores the result in a general-purpose register.

Note: The div instruction is supported only in the POWER architecture.

POWER
div RT,RA,RB
div. RT,RA,RB
divo RT,RA,RB
divo. RT,RA,RB

### Description

The div instruction concatenates the contents of general-purpose register (GPR) RA and the contents of Multiply Quotient (MQ) Register, divides the result by the contents of GPR RB, and stores the result in the target GPR RT. The remainder has the same sign as the dividend, except that a zero quotient or a zero remainder is always positive. The results obey the equation:

dividend = (divisor x quotient) + remainder

where a dividend is the original (RA) || (MQ), divisor is the original (RB), quotient is the final (RT), and remainder is the final (MQ).

For the case of -2**31 P -1 , the MQ Register is set to 0 and -2**31 is placed in GPR RT. For all other overflows, the contents of MQ, the target GPR RT, and the Condition Register Field 0 (if the Record Bit (Rc) is 1) are undefined.

The div instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

 Syntax Form Overflow Exception (OE) Fixed-Point Exception Register Record Bit (Rc) Condition Register Field 0 div 0 None 0 None div. 0 None 1 LT,GT,EQ,SO divo 1 SO,OV 0 None divo. 1 SO,OV 1 LT,GT,EQ,SO

The four syntax forms of the div instruction never affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction affects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

### Parameters

 RT Specifies target general-purpose register where result of operation is stored. RA Specifies source general-purpose register for operation. RB Specifies source general-purpose register for operation.

### Examples

1. The following code divides the contents of GPR 4, concatenated with the MQ Register, by the contents of GPR 6 and stores the result in GPR 4:
# Assume the MQ Register contains 0x0000 0001.
# Assume GPR 4 contains 0x0000 0000.
# Assume GPR 6 contains 0x0000 0002.
div 4,4,6
# GPR 4 now contains 0x0000 0000.
# The MQ Register now contains 0x0000 0001.
2. The following code divides the contents of GPR 4, concatenated with the MQ Register, by the contents of GPR 6, stores the result in GPR 4, and sets Condition Register Field 0 to reflect the result of the operation:
# Assume the MQ Register contains 0x0000 0002.
# Assume GPR 4 contains 0x0000 0000.
# Assume GPR 6 contains 0x0000 0002.
div. 4,4,6
# GPR 4 now contains 0x0000 0001.
# MQ Register contains 0x0000 0000.
3. The following code divides the contents of GPR 4, concatenated with the MQ Register, by the contents of GPR 6, places the result in GPR 4, and sets the Summary Overflow and Overflow bits in the Fixed-Point Exception Register to reflect the result of the operation:
# Assume GPR 4 contains 0x0000 0001.
# Assume GPR 6 contains 0x0000 0000.
# Assume the MQ Register contains 0x0000 0000.
divo 4,4,6
# GPR 4 now contains an undefined quantity.
# The MQ Register is undefined.
4. The following code divides the contents of GPR 4, concatenated with the MQ Register, by the contents of GPR 6, places the result in GPR 4, and sets the Summary Overflow and Overflow bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:
# Assume GPR 4 contains 0x-1.
# Assume GPR 6 contains 0x2.
# Assume the MQ Register contains 0xFFFFFFFF.
divo. 4,4,6
# GPR 4 now contains 0x0000 0000.
# The MQ Register contains 0x-1.

### Related Information

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