Fixed-Point Processor

The PowerPC fixed-point processor uses the following registers for nonprivileged instructions.

• Thirty-two 32-bit General-Purpose Registers (GPRs).
• One 32-bit Fixed-Point Exception Register.

The POWER fixed-point processor uses the following registers for nonprivileged instructions. These registers are:

• Thirty-two 32-bit GPRs
• One 32-bit Fixed-Point Exception Register
• One 32-bit Multiply-Quotient (MQ) Register

The GPRs are the principal internal storage mechanism in the fixed-point processor.

Fixed-Point Load and Store Instructions

The fixed-point load instructions move information from a location addressed by the effective address (EA) into one of the GPRs. The load instructions compute the EA when moving data. If the storage access does not cause an alignment interrupt or a data storage interrupt, the byte, halfword, or word addressed by the EA is loaded into a target GPR. See "Extended Mnemonics of Fixed-Point Load Instructions" for information on extended mnemonics for fixed-point load instructions.

The fixed-point store instructions perform the reverse function. If the storage access does not cause an alignment interrupt or a data storage interrupt, the contents of a source GPR are stored in the byte, halfword, or word in storage addressed by the EA.

In user programs, load and store instructions which access unaligned data locations (for example, an attempt to load a word which is not on a word boundary) will be executed, but may incur a performance penalty. Either the hardware performs the unaligned operation, or an alignment interrupt occurs and an operating system alignment interrupt handler is invoked to perform the unaligned operation.

Fixed-Point Load and Store with Update Instructions

Load and store instructions have an "update" form, in which the base GPR is updated with the EA in addition to the regular move of information from or to memory.

For POWER load instructions, there are four conditions which result in the EA not being saved in the base GPR:

1. The GPR to be updated is the same as the target GPR. In this case, the updated register contains data loaded from memory.
2. The GPR to be updated is GPR 0.
3. The storage access causes an alignment interrupt.
4. The storage access causes a data storage interrupt.

For POWER store instructions, conditions 2, 3, and 4 result in the EA not being saved into the base GPR.

For PowerPC load and store instructions, conditions 1 and 2 above result in an invalid instruction form.

In user programs, load and store with update instructions which access an unaligned data location will be performed by either the hardware or the alignment interrupt handler of the underlying operating system. An alignment interrupt will result in the EA not being in the base GPR.

Fixed-Point String Instructions

The Fixed-Point String instructions allow the movement of data from storage to registers or from registers to storage without concern for alignment. These instructions can be used for a short move between arbitrary storage locations or to initiate a long move between unaligned storage fields. Load String Indexed and Store String Indexed instructions of zero length do not alter the target register.

Fixed-Point Address Computation Instructions

There are several address computation instructions in POWER. These are merged into the arithmetic instructions for PowerPC.

Fixed-Point Arithmetic Instructions

The fixed-point arithmetic instructions treat the contents of registers as 32-bit signed integers. Several subtract mnemonics are provided as extended mnemonics of addition mnemonics. See "Extended Mnemonics of Fixed-Point Arithmetic Instructions" for information on these extended mnemonics.

There are differences between POWER and PowerPC for all of the fixed-point divide instructions and for some of the fixed-point multiply instructions. To assemble a program that will run on both architectures, the milicode routines for division and multiplication should be used. See "Using Milicode Routines" for information on the available milicode routines.

Fixed-Point Compare Instructions

The fixed-point compare instructions algebraically or logically compare the contents of register RA with one of the following:

• The sign-extended value of the SI field
• The UI field
• The contents of register RB

Algebraic comparison compares two signed integers. Logical comparison compares two unsigned integers.

There are different input operand formats for POWER and PowerPC. A new operand, the L field, is added for PowerPC. There are also invalid instruction form restrictions for PowerPC. The assembler checks for invalid instruction forms in PowerPC assembly modes.

Extended mnemonics for fixed-point compare instructions are discussed in "Extended Mnemonics of Fixed-Point Compare Instructions".

Fixed-Point Trap Instructions

Fixed-point trap instructions test for a specified set of conditions. Traps can be defined for events that should not occur during program execution, such as an index out of range or the use of an invalid character. If a defined trap condition occurs, the system trap handler is invoked to handle a program interruption. If the defined trap conditions do not occur, normal program execution continues.

The contents of register RA are compared with the sign-extended SI field or with the contents of register RB, depending on the particular trap instruction. In 32-bit implementations, only the contents of the low-order 32 bits of registers RA and RB are used in the comparison.

The comparison results in five conditions that are ANDed with the TO field. If the result is not 0, the system trap handler is invoked. The five resulting conditions are:

Extended mnemonics for the most useful TO field values are provided, and a standard set of codes is provided for the most common combinations of trap conditions. See "Extended Mnemonics of Fixed-Point Trap Instructions" for information on these extended mnemonics and codes.

Fixed-Point Logical Instructions

Fixed-point logical instructions perform logical operations in a bit-wise fashion. The extended mnemonics for the no-op instruction and the OR and NOR instructions are discussed in "Extended Mnemonics of Fixed-Point Logical Instructions".

Fixed-Point Rotate and Shift Instructions

The fixed-point processor performs rotate operations on data from a GPR. These instructions rotate the contents of a register in one of the following ways:

• The result of the rotation is inserted into the target register under the control of a mask. If the mask bit is 1, the associated bit of the rotated data is placed in the target register. If the mask bit is 0, the associated data bit in the target register is unchanged.
• The result of the rotation is ANDed with the mask before being placed into the target register.

The rotate left instructions allow (in concept) right-rotation of the contents of a register. For 32-bit implementations, an n-bit right-rotation can be performed by a left-rotation of 32-n.

The fixed-point shift instructions logically perform left and right shifts. The result of a shift instruction is placed in the target register under the control of a generated mask.

Some POWER shift instructions involve the MQ register. This register is also updated.

Extended mnemonics are provided for extraction, insertion, rotation, shift, clear, and clear left and shift left operations. See "Extended Mnemonics of Fixed-Point Rotate and Shift Instructions" for information on these mnemonics.

Fixed-Point Move to or from Special-Purpose Registers Instructions

Several instructions move the contents of one Special-Purpose Register (SPR) into another SPR or into a General-Purpose Register (GPR). These instructions are supported by a set of extended mnemonics that have each SPR encoding incorporated into the extended mnemonic. These include both nonprivileged and privileged instructions.

Note: The SPR field length is 10 bits for PowerPC and 5 bits for POWER. To maintain source-code compatibility for POWER and PowerPC, the low-order 5 bits and high-order 5 bits of the SPR number must be reversed prior to being used as the input operand to the mfspr instruction or the mtspr instruction. The numbers defined in the encoding tables for the mfspr and mtspr instructions have already had their low-order 5 bits and high-order 5 bits reversed. When using the dbx command to debug a program, remember that the low-order 5 bits and high-order 5 bits of the SPR number are reversed in the output from the dbx command.

There are different sets of SPRs for POWER and PowerPC. Encodings for the same SPRs are identical for POWER and PowerPC except for moving from the DEC (Decrement) SPR.

Moving from the DEC SPR is privileged in PowerPC, but nonprivileged in POWER. One bit in the SPR field is 1 for privileged operations, but 0 for nonprivileged operations. Thus, the encoding number for the DEC SPR for the mfdec instruction has different values in PowerPC and POWER. The DEC encoding number is 22 for PowerPC and 6 for POWER. If the mfdec instruction is used, the assembler determines the DEC encoding based on the current assembly mode. The following list shows the assembler processing of the mfdec instruction for each assembly mode value:

• If the assembly mode is pwr, pwr2, or 601, the DEC encoding is 6.
• If the assembly mode is ppc, 603, or 604, the DEC encoding is 22.
• If the default assembly mode, which treats POWER/PowerPC incompatibility errors as instructional warnings, is used, the DEC encoding is 6. Instructional warning 158 reports that the DEC SPR encoding 6 is used to generate the object code. The warning can be suppressed with the -W flag.
• If the assembly mode is any, the DEC encoding is 6. If the -w flag is used, a warning message (158) reports that the DEC SPR encoding 6 is used to generate the object code.
• If the assembly mode is com, an error message reports that the mfdec instruction is not supported. No object code is generated. In this situation, the mfspr instruction must be used to encode the DEC number.

For more information on SPR encodings, see "Extended Mnemonics of Moving from or to Special-Purpose Registers".

Related Information

Processing and Storage: Overview.

Overview of POWER and PowerPC Architecture.

Branch Processor.

Floating-Point Processor.

PowerPC Architecture.