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Assembler Language Reference

svc (Supervisor Call) Instruction

Purpose

Generates a supervisor call interrupt.

Note: The svc instruction is supported only in the POWER family architecture.

Syntax

Bits Value
0-5 17
6-10 ///
11-15 ///
16-19 FLI
20-26 LEV
27-29 FL2
30 SA
31 LK
POWER family 
svc LEV, FL1, FL2
svcl LEV, FL1, FL2
Bits Value
0-5 17
6-10 ///
11-15 ///
16-29 SV
30 SA
31 LK
svca SV
svcla SV

Description

The svc instruction generates a supervisor call interrupt and places bits 16-31 of the svc instruction into bits 0-15 of the Count Register (CR) and bits 16-31 of the Machine State Register (MSR) into bits 16-31 of the CR.

Consider the following when using the svc instruction:

The svc instruction has four syntax forms. Each syntax form affects the MSR.

Syntax Form Link Bit (LK) SVC Absolute Bit (SA) Machine State Register Bits
svc 0 0 EE,PR,FE set to zero
svcl 1 0 EE,PR,FE set to zero
svca 0 1 EE,PR,FE set to zero
svcla 1 1 EE,PR,FE set to zero

The four syntax forms of the svc instruction never affect the FP, ME, AL, IP, IR, or DR bits of the MSR. The EE, PR, and FE bits of the MSR are always set to 0. The Fixed-Point Exception Register and Condition Register Field 0 are unaffected by the svc instruction.

Parameters

LEV Specifies execution address.
FL1 Specifies field for optional data passing to SVC routine.
FL2 Specifies field for optional data passing to SVC routine.
SV Specifies field for optional data passing to SVC routine.

Related Information

The cror (Condition Register OR) instruction, sc (System Call) instruction.

Branch Processor .

System Call Instructions .

Functional Differences for POWER family and PowerPC Instructions .

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