Assembler Language Reference

subfze or sfze (Subtract from Zero Extended) Instruction

Purpose

Adds the one's complement of the contents of a general-purpose register, the Carry bit in the Fixed-Point Exception Register, and 0 and places the result in a second general-purpose register.

Syntax

Bits	Value
0-5	31
6-10	RT
11-15	RA
16-20	///
21	OE
22-30	200
31	Rc

PowerPC
subfze	RT, RA
subfze.	RT, RA
subfzeo	RT, RA
subfzeo.	RT, RA

POWER family
sfze	RT, RA
sfze.	RT, RA
sfzeo	RT, RA
sfzeo.	RT, RA

Description

The subfze and sfze instructions add the one's complement of the contents of general-purpose register (GPR) RA, the Carry bit of the Fixed-Point Exception Register, and x'00000000' and store the result in the target GPR RT.

The subfze instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The sfze instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
subfze	0	CA	0	None
subfze.	0	CA	1	LT,GT,EQ,SO
subfzeo	1	SO,OV,CA	0	None
subfzeo.	1	SO,OV,CA	1	LT,GT,EQ,SO
sfze	0	CA	0	None
sfze.	0	CA	1	LT,GT,EQ,SO
sfzeo	1	SO,OV,CA	0	None
sfzeo.	1	SO,OV,CA	1	LT,GT,EQ,SO

The four syntax forms of the subfze instruction, and the four syntax forms of the sfze instruction, always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction effects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RT	Specifies target general-purpose register where result of operation is stored.
RA	Specifies source general-purpose register for operation.

Examples

The following code adds the one's complement of the contents of GPR 4, the Carry bit, and zero and stores the result in GPR 6:
```
# Assume GPR 4 contains 0x9000 3000.
# Assume the Carry bit is set to one.
subfze 6,4
# GPR 6 now contains 0x6FFF D000.
```

The following code adds the one's complement of the contents of GPR 4, the Carry bit, and zero, stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0xB004 3000.
# Assume the Carry bit is set to one.
subfze. 6,4
# GPR 6 now contains 0x4FFB D000.
```

The following code adds the one's complement of the contents of GPR 4, the Carry bit, and zero, stores the result in GPR 6, and sets the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0xEFFF FFFF.
# Assume the Carry bit is set to zero.
subfzeo 6,4
# GPR 6 now contains 0x1000 0000.
```

The following code adds the one's complement of the contents of GPR 4, the Carry bit, and zero, stores the result in GPR 6, and sets Condition Register Field 0 and the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0x70FB 6500.
# Assume the Carry bit is set to zero.
subfzeo 6,4
# GPR 6 now contains 0x8F04 9AFF.
```

Related Information

Fixed-Point Processor .

Fixed-Point Arithmetic Instructions .