The PowerPC instruction, sync, ensures that all previous instructions have completed before the next instruction is initiated.
The POWER family instruction, dcs, causes the processor to wait until all data cache lines have been written.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-9 | /// |
| 10 | L |
| 11-15 | /// |
| 16-20 | /// |
| 21-30 | 598 |
| 31 | / |
| PowerPC | |
|---|---|
| sync | L |
| POWER family | |
|---|---|
| dcs | |
The PowerPC instruction, sync, provides an ordering function that ensures that all instructions initiated prior to the sync instruction complete, and that no subsequent instructions initiate until after the sync instruction completes. When the sync instruction completes, all storage accesses initiated prior to the sync instruction are complete.
The L field is used to specify a heavyweight sync (L = 0) or a lightweight sync (L = 1).
The POWER family instruction, dcs, causes the processor to wait until all data cache lines being written or scheduled for writing to main memory have finished writing.
The dcs and sync instructions have one syntax form and do not affect the Fixed-Point Exception Register. If the Record (Rc) bit is set to 1, the instruction form is invalid.
| L | Specifies heavyweight or a lightweight sync. |
The following code makes the processor wait until the result of the dcbf instruction is written into main memory:
# Assume that GPR 4 holds 0x0000 3000. dcbf 1,4 sync # Wait for memory to be updated.
eieio (Enforce In-Order Execution of I/O) Instruction.