Allows a program to request a cache block fetch before it is actually needed by the program.
Note: The dcbtst instruction is supported only in the PowerPC architecture.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | /// |
| 11-15 | RA |
| 16-20 | RB |
| 21-30 | 246 |
| 31 | / |
| PowerPC | |
|---|---|
| dcbtst | RA, RB |
The dcbtst instruction improves performance by anticipating a store to the addressed byte. The block containing the byte addressed by the effective address (EA) is fetched into the data cache before the block is needed by the program. The program can later perform stores to the block and may not experience the added delay caused by fetching the block into the cache. Executing the dcbtst instruction does not invoke the system error handler.
The dcbtst instruction calculates an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. If the RA field is 0, EA is the sum of the contents of RB and 0.
Consider the following when using the dcbtst instruction:
The dcbtst instruction has one syntax form and does not affect Condition Register field 0 or the Fixed-Point Exception register.
| RA | Specifies source general-purpose register for operation. |
| RB | Specifies source general-purpose register for operation. |
The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.