Assembler Language Reference

clf (Cache Line Flush) Instruction

Purpose

Writes a line of modified data from the data cache to main memory, or invalidates cached instructions or unmodified data.

Note: The clf instruction is supported only in the POWER family architecture.

Syntax

Description

The clf instruction calculates an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. If the RA field is 0, EA is the sum of the contents of RB and 0. If the RA field is not 0 and if the instruction does not cause a data storage interrupt, the result of the operation is placed back into GPR RA.

Consider the following when using the clf instruction:

• If the Data Relocate (DR) bit of the Machine State Register (MSR) is set to 0, the effective address is treated as a real address.
• If the MSR DR bit is set to 1, the effective address is treated as a virtual address. The MSR Instruction Relocate bit (IR) is ignored in this case.
• If a line containing the byte addressed by the EA is in the data cache and has been modified, writing the line to main memory is begun. If a line containing the byte addressed by EA is in one of the caches, the line is not valid.
• When MSR (DR) = 1, if the virtual address has no translation, a Data Storage interrupt occurs, setting the first bit of the Data Storage Interrupt Segment register to 1.
• A machine check interrupt occurs when the virtual address translates to an invalid real address and the line exists in the data cache.
• Address translation treats the instruction as a load to the byte addressed, ignoring protection and data locking. If this instruction causes a Translation Look-Aside buffer (TLB) miss, the reference bit is set.
• If the EA specifies an I/O address, the instruction is treated as a no-op, but the EA is placed in GPR RA.

The clf instruction has one syntax form and does not effect the Fixed-Point Exception register. If the Record (Rc) bit is set to 1, Condition Register Field 0 is undefined.

Parameters

Examples

The processor is not required to keep instruction storage consistent with data storage. The following code executes storage synchronization instructions prior to executing an modified instruction:

# Assume that instruction A is assigned to storage location
# ox0033 0020.
# Assume that the storage location to which A is assigned
# contains 0x0000 0000.
# Assume that GPR 3 contains 0x0000 0020.
# Assume that GPR 4 contains 0x0033 0020.
# Assume that GPR 5 contains 0x5000 0020.
st      R5,R4,R3         # Store branch instruction in memory
clf     R4,R3            # Flush A from cache to main memory
dcs                      # Ensure clf is complete
ics                      # Discard prefetched instructions
b       0x0033 0020      # Go execute the new instructions

After the store, but prior to the execution of the clf, dcs, and ics instructions, the copy of A in the cache contains the branch instruction. However, it is possible that the copy of A in main memory still contains 0. The clf instruction copies the new instruction back to main memory and invalidates the cache line containing location A in both the instruction and data caches. The sequence of the dcs instruction followed by the ics instruction ensures that the new instruction is in main memory and that the copies of the location in the data and instruction caches are invalid before fetching the next instruction.

Related Information

The clcs (Cache Line Compute Size) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.

Processing and Storage: Overview.