Invalidates a block containing the byte addressed in the data cache, causing subsequent references to retrieve the block again from main memory.
Note: The dcbi instruction is supported only in the PowerPC architecture.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | /// |
| 11-15 | RA |
| 16-20 | RB |
| 21-30 | 470 |
| 31 | / |
| PowerPC | |
|---|---|
| dcbi | RA, RB |
If the contents of general-purpose register (GPR) RA is not 0, the dcbi instruction computes an effective address (EA) by adding the contents of GPR RA to the contents of GPR RB. Otherwise, the EA is the content of GPR RB.
If the cache block containing the addressed byte is in the data cache, the block is made invalid. Subsequent references to a byte in the block cause a reference to main memory.
The dcbi instruction is treated as a store to the addressed cache block with respect to protection.
The dcbi instruction has only one syntax form and does not effect the Fixed-Point Exception register.
| RA | Specifies the source general-purpose register for EA computation. |
| RB | Specifies the source general-purpose register for EA computation. |
The dcbi instruction is privileged.
The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, cli (Cache Line Invalidate) instruction, dcbf (Data Cache Block Flush) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.