Assembler Language Reference

cli (Cache Line Invalidate) Instruction

Purpose

Invalidates a line containing the byte addressed in either the data or instruction cache, causing subsequent references to retrieve the line again from main memory.

Note: The cli instruction is supported only in the POWER family architecture.

Syntax

Bits	Value
0-5	31
6-10	///
11-15	RA
16-20	RB
21-30	502
31	Rc

POWER family
cli	RA, RB

Description

The cli instruction invalidates a line containing the byte addressed in either the data or instruction cache. If RA is not 0, the cli instruction calculates an effective address (EA) by adding the contents of general-purpose register (GPR) RA to the contents of GPR RB. If RA is not GPR 0 or the instruction does not cause a Data Storage interrupt, the result of the calculation is placed back into GPR RA.

Consider the following when using the cli instruction:

If the Data Relocate (DR) bit of the Machine State Register (MSR) is 0, the effective address is treated as a real address.

If the MSR DR bit is 1, the effective address is treated as a virtual address. The MSR Relocate (IR) bit is ignored in this case.

If a line containing the byte addressed by the EA is in the data or instruction cache, the line is made unusable so the next reference to the line is taken from main memory.

When MSR (DR) =1, if the virtual address has no translation, a Data Storage interrupt occurs, setting the first bit of the Data Storage Interrupt Segment Register to 1.

Address translation treats the cli instruction as a store to the byte addressed, ignoring protection and data locking. If this instruction causes a Translation Look-Aside buffer (TLB) miss, the reference bit is set.

If the EA specifies an I/O address, the instruction is treated as a no-op, but the EA is still placed in RA.

The cli instruction has only one syntax form and does not effect the Fixed-Point Exception Register. If the Record (Rc) bit is set to 1, the Condition Register Field 0 is undefined.

Parameters

RA	Specifies the source general-purpose register for EA calculation and possibly the target general-purpose register (when RA is not GPR 0) for operation.
RB	Specifies the source general-purpose register for EA calculation.

Security

The cli instruction is privileged.

Related Information

The clcs (Cache Line Compute Size) instruction, clf (Cache Line Flush) instruction, dcbf (Data Cache Block Flush) instruction, dcbi (Data Cache Block Invalidate) instruction, dcbst (Data Cache Block Store) instruction, dcbt (Data Cache Block Touch) instruction, dcbtst (Data Cache Block Touch for Store) instruction, dcbz or dclz (Data Cache Block Set to Zero) instruction, dclst (Data Cache Line Store) instruction, icbi (Instruction Cache Block Invalidate) instruction, sync (Synchronize) or dcs (Data Cache Synchronize) instruction.

Processing and Storage: Overview.