Assembler Language Reference

POWER family and PowerPC Architecture Overview

A POWER family or PowerPC microprocessor contains the sequencing and processing controls for instruction fetch, instruction execution, and interrupt action, and implements the instruction set, storage model, and other facilities defined in the POWER family and PowerPC architectures.

A POWER family or PowerPC microprocessor contains a branch processor, a fixed-point processor, and a floating-point processor. The microprocessor can execute the following classes of instructions:

• Branch instructions
• Fixed-point instructions
• Floating-point instructions

The following diagram illustrates a logical representation of instruction processing for the PowerPC microprocessor.

Figure 1. Logical Processing Model. The process begins at the top with Branch Processing, which branches to either fixed-point or float-point processing. These processes send and receive data from storage. Storage will also send more instructions to Branch Processing at the top of the diagram.

The following table shows the registers for the PowerPC user instruction set architecture. These registers are in the CPU that are used for 32-bit applications and are available to the user.

The following table shows the registers of the POWER family user instruction set architecture. These registers are in the CPU that are used for 32-bit applications and are available to the user.

The processing unit is a word-oriented, fixed-point processor functioning in tandem with a doubleword-oriented, floating-point processor. The microprocessor uses 32-bit word-aligned instructions. It provides for byte, halfword, and word operand fetches and stores for fixed point, and word and doubleword operand fetches and stores for floating point. These fetches and stores can occur between main storage and a set of 32 general-purpose registers, and between main storage and a set of 32 floating-point registers.

Instruction Forms

All instructions are four bytes long and are word-aligned. Therefore, when the processor fetches instructions (for example, branch instructions), the two low-order bits are ignored. Similarly, when the processor develops an instruction address, the two low-order bits of the address are 0.

Bits 0-5 always specify the op code. Many instructions also have an extended op code (for example, XO-form instructions). The remaining bits of the instruction contain one or more fields. The alternative fields for the various instruction forms are shown in the following:

• I Form

  Bits	Value
  0-5	OPCD
  6-29	LI
  30	AA
  31	LK

• B Form

  Bits	Value
  0-5	OPCD
  6-10	BO
  11-15	BI
  16-29	BD
  30	AA
  31	LK

• SC Form

  Bits	Value
  0-5	OPCD
  6-10	///
  11-15	///
  16-29	///
  30	XO
  31	/

• D Form

  Bits	Value
  0-5	OPCD
  6-10	RT, RS, FRT, FRS, TO, or BF, /, and L
  11-15	RA
  16-31	D, SI, or UI

• DS Form

  Bits	Value
  0-5	OPCD
  6-10	RT or RS
  11-15	RA
  16-29	DS
  30-31	XO

• X Instruction Format

  Bits	Value
  0-5	OPCD
  6-10	RT, FRT, RS, FRS, TO, BT, or BF, /, and L
  11-15	RA, FRA, SR, SPR, or BFA and //
  16-20	RB, FRB, SH, NB, or U and /
  21-30	XO or EO
  31	Rc

  • XL Instruction Format

    Bits	Value
    0-5	OPCD
    6-10	RT or RS
    11-20	spr or /, FXM and /
    21-30	XO or EO
    31	Rc

  • XFX Instruction Format

    Bits	Value
    0-5	OPCD
    6-10	RT or RS
    11-20	spr or /, FXM and /
    21-30	XO or EO
    31	Rc

  • XFL Instruction Format

    Bits	Value
    0-5	OPCD
    6	/
    7-14	FLM
    15	/
    16-20	FRB
    21-30	XO or EO
    31	Rc

  • XO Instruction Format

    Bits	Value
    0-5	OPCD
    6-10	RT
    11-15	RA
    16-20	RB
    21	OE
    22-30	XO or EO
    31	Rc

• A Form

  Bits	Value
  0-5	OPCD
  6-10	FRT
  11-15	FRA
  16-20	FRB
  21-25	FRC
  26-30	XO
  31	Rc

• M Form

  Bits	Value
  0-5	OPCD
  6-10	RS
  `11-15	RA
  16-20	RB or SH
  21-25	MB
  26-30	ME
  31	Rc

For some instructions, an instruction field is reserved or must contain a particular value. This is not indicated in the previous figures, but is shown in the syntax for instructions in which these conditions are required. If a reserved field does not have all bits set to 0, or if a field that must contain a particular value does not contain that value, the instruction form is invalid. See Detection Error Conditions for more information on invalid instruction forms.

Split-Field Notation

In some cases an instruction field occupies more than one contiguous sequence of bits, or occupies a contiguous sequence of bits that are used in permuted order. Such a field is called a split field. In the previous figures and in the syntax for individual instructions, the name of a split field is shown in lowercase letters, once for each of the contiguous bit sequences. In the description of an instruction with a split field, and in certain other places where the individual bits of a split field are identified, the name of the field in lowercase letters represents the concatenation of the sequences from left to right. In all other cases, the name of the field is capitalized and represents the concatenation of the sequences in some order, which does not have to be left to right. The order is described for each affected instruction.

Instruction Fields

Let mstart=MB and mstop=ME:
If mstart < mstop + 1 then
          mask(mstart..mstop) = ones
          mask(all other) = zeros
If mstart = mstop + 1 then
          mask(0:31) = ones
If mstart > mstop + 1 then
          mask(mstop+1..mstart-1) = zeros
          mask(all other) = ones

Related Information

Processing and Storage.

Branch Processor.

Fixed-Point Processor.

Floating-Point Processor.