Assembler Language Reference

Features of the AIX Assembler

This section describes features of the AIX assembler.

Multiple Hardware Architecture and Implementation Platform Support

The assembler supports the following systems:

• Systems using the first-generation POWER family processors (POWER family architecture).
• Systems using the POWER2 processors (POWER family architecture).
• Systems using the PowerPC 601 RISC Microprocessor, PowerPC 604 RISC Microprocessor, or the PowerPC A35 RISC Microprocessor (PowerPC architecture).

The assembler also supports development of programs for the PowerPC 603 RISC Microprocessor (PowerPC architecture).

There are several categories of instructions. The following table lists the categories of instructions and shows which implementations support each instruction category. The "X" means the implementation supports the instruction category.

The following abbreviations are used in the heading of the previous table:

Host Machine Independence and Target Environment Indicator Flag

The host machine is the hardware platform on which the assembler runs. The target machine is the platform on which the object code is run. The assembler can assemble a source program for any target machine, regardless of the host machine on which the assembler runs.

The target machine can be specified by using either the assembly mode option flag -m of the as command or the .machine pseudo-op. If neither the -m flag nor the .machine pseudo-op is used, the default assembly mode is used. If both the -m flag and a .machine pseudo-op are used, the .machine pseudo-op overrides the -m flag. Multiple .machine pseudo-ops are allowed in a source program. The value in a later .machine pseudo-op overrides a previous .machine pseudo-op.

The default assembly mode provided by the AIX assembler has the POWER family/PowerPC intersection as the target environment, but treats all POWER/PowerPC incompatibility errors (including instructions outside the POWER/PowerPC intersection and invalid form errors) as instructional warnings. The -W and -w assembler flags control whether these warnings are displayed. In addition to being closen by the absence of the -m flag of the as command or the .machine pseudo-op, the default assembly mode can also be explicitly specified with the -m flag of the as command or with the .machine pseudo-op.

To assemble a source program containing platform-unique instructions from more than one platform without errors or warnings, use one of the following methods:

• Use the .machine pseudo-op in the source program.
• Assemble the program with the assembly mode set to the any mode (with the -m flag of the as command).

For example, the source code cannot contain both POWER family-unique instructions and PowerPC 601 RISC Microprocessor-unique instructions. This is also true for each of the sub-source programs contained in a single source program. A sub-source program begins with a .machine pseudo-op and ends before the next .machine pseudo-op. Since a source program can contain multiple .machine pseudo-ops, it normally consists of several sub-source programs. For more information, see the .machine pseudo-op.

Mnemonics Cross-Reference

The assembler supports both PowerPC and POWER family mnemonics. The assembler listing has a cross-reference for both mnemonics. The cross-reference is restricted to instructions that have different mnemonics in the POWER family and PowerPC architectures, but which share the same op codes, functions, and operand input formats.

The assembler listing contains a column to display mnemonics cross-reference information. For more information on the assembler listing, see Interpreting an Assembler Listing.

The mnemonics cross-reference helps the user migrate a source program from one architecture to another. The -s flag for the as command provides a mnemonics cross-reference in the assembler listing to assist with migration. If the -s flag is not used, no mnemonics cross-reference is provided.

CPU ID Definition

During the assembly process the assembler determines which instruction set (from a list of several complete instruction sets defined in the architectures or processor implementations) is the smallest instruction set containing all the instructions used in the program. The program is given a CPU ID value indicating this instruction set. Therefore a CPU ID indicates the target environment on which the object code can be run. The CPU ID value for the program is an assembler output value included in the XCOFF object file generated by the assembler.

CPU ID can have the following values:

The assembler output value CPU ID is not the same thing as the assembly mode. The assembly mode (determined by the -m flag of the as command and by use of the .machine pseudo-op in the program) determines which instructions the assembler accepts without errors or warnings. The CPU ID is an output value indicating which instructions are actually used.

In the output XCOFF file, the CPU ID is stored in the low-order byte of the n_type field in a symbol table entry with the C_FILE storage class. The following list shows the low-order byte values and corresponding CPU IDs:

Source Language Type

For cascade compilers, the assembler records the source-language type. In the XCOFF file, the high-order byte of the n_type field of a symbol table entry with the C_FILE storage class holds the source language type information. The following language types are defined:

The source language type is indicated by the .source pseudo-op. By default, the source-language type is "Assembler." For more information, see the .source pseudo-op.

Detection Error Conditions

Error number 149 is reported if the source program contains instructions that are not supported in the intended target environment.

An error is reported if the source program contains invalid instruction forms. This error occurs due to incompatibilities between the POWER family and PowerPC architectures. Some restrictions that apply in the PowerPC architecture do not apply in the POWER family architecture. According to the PowerPC architecture, the following invalid instruction forms are defined:

• If an Rc bit, LK bit, or OE bit is defined as / (slash) but coded as 1, or is defined as 1 but coded as 0, the form is invalid. Normally, the assembler ensures that these bits contain correct values.

  Some fields are defined with more than one / (slash) (for example, "///"). If they are coded as nonzero, the form is invalid. If certain input operands are used for these fields, they must be checked. For this reason, the following instructions are checked:

  • For the PowerPC System Call instructions or the POWER family Supervisor Call instructions, if the POWER family svca mnemonic is used when the assembly mode is PowerPC type, the SV field must be 0. Otherwise, the instruction form is invalid and error number 165 is reported.
    Note
    The svc and svcl instructions are not supported in PowerPC target modes. The svcla instruction is supported only on the PowerPC 601 RISC Microprocessor.
  • For the Move to Segment Register Indirect instruction, if the POWER family mtsri mnemonic is used in PowerPC target modes, the RA field must be 0. Otherwise, the instruction form is invalid and error number 154 is reported. If the PowerPC mtsrin mnemonic is used in PowerPC target modes, it requires only two input operands, so no check is needed.
• For all of the Branch Conditional instructions (including Branch Conditional, Branch Conditional to Link Register, and Branch Conditional to Count Register), bits 0-3 of the BO field are checked. If the bits that are required to contain 0 contain a nonzero value, error 150 is reported.

  The encoding for the BO field is defined in the section "Branch Processor Instructions" of PowerPC architecture. The following list gives brief descriptions of the possible values for this field:

  BO	Description
  0000y	Decrement the Count Register (CTR); then branch if the value of the decremented CTR is not equal to 0 and the condition is False.
  0001y	Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is False.
  001zy	Branch if the condition is False.
  0100y	Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is True.
  0101y	Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is True.
  011zy	Branch if the condition is True.
  1z00y	Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0.
  1z01y	Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0.
  1z1zz	Branch always. The z bit denotes a bit that must be 0. If the bit is not 0, the instruction form is invalid.

  Note
  The y bit provides a hint about whether a conditional branch is likely to be taken. The value of this bit can be either 0 or 1. The default value is 0. The extended mnemonics for Branch Prediction as defined in PowerPC architecture are used to set this bit to 0 or 1. (See Extended Mnemonics for Branch Prediction for more information.)

  Branch always instructions do not have a y bit in the BO field. Bit 4 of the BO field should contain 0. Otherwise, the instruction form is invalid.

  The third bit of the BO field is specified as the "decrement and test CTR" option. For Branch Conditional to Count Register instructions, the third bit of the BO field must not be 0. Otherwise, the instruction form is invalid and error 163 is reported.

• For the update form of fixed-point load instructions, the PowerPC architecture requires that the RA field not be equal to either 0 or the RT field value. Otherwise, the instruction form is invalid and error number 151 is reported.

  This restriction applies to the following instructions:

  • lbzu
  • lbzux
  • lhzu
  • lhsux
  • lhau
  • lhaux
  • lwzu (lu in POWER family)
  • lwzux (lux in POWER family)
• For the update form of fixed-point store instructions and floating-point load and store instructions, the following instructions require only that the RA field not be equal to 0. Otherwise, the instruction form is invalid and error number 166 is reported.
  • lfsu
  • lfsux
  • lfdu
  • lfdux
  • stbu
  • stbux
  • sthu
  • sthux
  • stwu (stu in POWER family)
  • stwux (stux in POWER family)
  • stfsu
  • stfux
  • stfdu
  • stfdux
• For multiple register load instructions, the PowerPC architecture requires that the RA field and the RB field, if present in the instruction format, not be in the range of registers to be loaded. Also, RA=RT=0 is not allowed. If RA=RT=0, the instruction form is invalid and error 164 is reported. This restriction applies to the following instructions:
  • lmn (lm in POWER family)
  • lswi (lsi in POWER family)
  • lswx (lsx in POWER family)
    Note
    For the lswx instruction, the assembler only checks whether RA=RT=0, because the load register range is determined by the content of the XER register at run time.
• For fixed-point compare instructions, the PowerPC architecture requires that the L field be equal to 0. Otherwise, the instruction form is invalid and error number 154 is reported. This restriction applies to the following instructions:
  • cmp
  • cmpi
  • cmpli
  • cmpl
    Note
    If the target mode is com, or ppc, the assembler checks the update form of fixed-point load instructions, update form of fixed-point store instructions, update form of floating-point load and store instructions, multiple-register load instructions, and fixed-point compare instructions, and reports any errors. If the target mode is any, pwr, pwr2, or 601, no check is performed.

Warning Messages

Warning messages are listed when the -w flag is used with the as command. Some warning messages are related to instructions with the same op code for POWER family and PowerPC:

• Several instructions have the same op code in both POWER family and PowerPC architectures, but have different functional definitions. The assembler identifies these instructions and reports warning number 153 when the target mode is com and the -w flag of the as command is used. Because these mnemonics differ functionally, they are not listed in the mnemonics cross-reference of the assembler listing generated when the -s flag is used with the as command. The following table lists these instructions.

  Table 1. Same Op Codes with Different Mnemonics

  POWER family	PowerPC
  dcs	sync
  ics	isync
  svca	sc
  mtsri	mtsrin
  lsx	lswx

• The following instructions have the same mnemonics and op code, but have different functional definitions in the POWER family and PowerPC architectures. The assembler cannot check for these, because the differences are not based on the machine the instructions execute on, but rather on what protection domain the instructions are running in.
  • mfsr
  • mfmsr
  • mfdec

Special-Purpose Register Changes and Special-Purpose Register Field Handling

TID, MQ, SDR0, RTCU, and RTCL are special-purpose registers (SPRs) defined in the POWER family architecture. They are not valid in the PowerPC architecture. However, MQ, RTCU, and RTCL are still available in the PowerPC 601 RISC Microprocessor.

DBATL, DBATU, IBATL, IBATU, TBL, and TBU are SPRs defined in the PowerPC architecture. They are not supported for the PowerPC 601 RISC Microprocessor. The PowerPC 601 RISC Microprocessor uses the BATL and BATU SPRs instead.

The assembler provides the extended mnemonics for "move to or from SPR" instructions. The extended mnemonics include all the SPRs defined in the POWER family and PowerPC architectures. An error is generated if an invalid extended mnemonic is used. The assembler does not support extended mnemonics for any of the following:

• POWER2-unique SPRs (IMR, DABR, DSAR, TSR, and ILCR)
• PowerPC 601 RISC Microprocessor-unique SPRs (HID0, HID1, HID2, HID5, PID, BATL, and BATU)
• PowerPC 603 RISC Microprocessor-unique SPRs (DMISS, DCMP, HASH1, HASH2, IMISS, ICMP, RPA, HID0, and IABR)
• PowerPC 604 RISC Microprocessor-unique SPRs (PIE, HID0, IABR, and DABR)

The assembler does not check the SPR field's encoding value for the mtspr and mfspr instructions, because the SPR encoding codes could be changed or reused. However, the assembler does check the SPR field's value range. If the target mode is pwr, pwr2, or com, the SPR field has a 5-bit length and a maximum value of 31. Otherwise, the SPR field has a 10-bit length and a maximum value of 1023.

To maintain source-code compatibility of the POWER family and PowerPC architectures, the assembler assumes that the low-order 5 bits and high-order 5 bits of the SPR number are reversed before they are used as the input operands to the mfspr or mtspr instruction.

Related Information

Assembler Overview.

Assembler Installation.

Assembling and Linking a Program.

Pseudo-ops Overview.

The as command.

.machine Pseudo-op, .source Pseudo-op.