Assembler Language Reference

rlwnm or rlnm (Rotate Left Word Then AND with Mask) Instruction

Purpose

Rotates the contents of a general-purpose register to the left by the number of bits specified in another general-purpose register, logically ANDs the rotated data with the generated mask, and stores the result in a third general-purpose register.

Syntax

Bits	Value
0-5	23
6-10	RS
11-15	RA
16-20	RB
21-25	MB
26-30	ME
31	Rc

PowerPC
rlwnm	RA, RS, RB, MB, ME
rlwnm.	RA, RS, RB, MB, ME
rlwnm	RA, RS, SH, BM
rlwnm.	RA, RS, SH, BM

POWER family
rlnm	RA, RS, RB, MB, ME
rlnm.	RA, RS, RB, MB, ME
rlnm	RA, RS, SH, BM
rlnm.	RA, RS, SH, BM

See Extended Mnemonics of Fixed-Point Rotate and Shift Instructions for more information.

Description

The rlwnm and rlnm instructions rotate the contents of the source general-purpose register (GPR) RS to the left by the number of bits specified by bits 27-31 of GPR RB, logically AND the rotated data with a 32-bit generated mask defined by the values in Mask Begin (MB) and Mask End (ME), and store the result in GPR RA.

Consider the following when using the rlwnm and rlnm instructions:

If the MB value is less than the ME value + 1, then the mask bits between and including the starting point and the end point are set to ones. All other bits are set to zeros.

If the MB value is the same as the ME value + 1, then all 32 mask bits are set to ones.

If the MB value is greater than the ME value + 1, then all of the mask bits between and including the ME value +1 and the MB value - 1 are set to zeros. All other bits are set to ones.

The BM parameter can also be used to specify the mask for these instructions. The assembler will generate the MB and ME parameters from the BM value.

The rlwnm and rlnm instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
rlwnm	None	None	0	None
rlwnm.	None	None	1	LT,GT,EQ,SO
rlnm	None	None	0	None
rlnm.	None	None	1	LT,GT,EQ,SO

The syntax forms of the rlwnm and rlnm instructions never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instructions affect the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA	Specifies target general-purpose register where result of operation is stored.
RS	Specifies source general-purpose register for operation.
RB	Specifies general-purpose register that contains number of bits for rotation of data.
MB	Specifies begin value of mask for operation.
ME	Specifies end value of mask for operation.
SH	Specifies shift value for operation.
BM	Specifies value of 32-bit mask.

Examples

The following code rotates the contents of GPR 4 to the left by 2 bits, logically ANDs the result with a mask of 29 ones, and stores the result in GPR 6:

# Assume GPR 4 contains 0x9000 3000.
# Assume GPR 5 contains 0x0000 0002.
# Assume GPR 6 contains 0xFFFF FFFF.
rlwnm 6,4,5,0,0x1D
# GPR 6 now contains 0x4000 C000.
# Under the same conditions
#  rlwnm 6,4,5,0xFFFFFFFC
# will produce the same result.

The following code rotates GPR 4 to the left by 2 bits, logically ANDs the result with a mask of 29 ones, stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:

# Assume GPR 4 contains 0xB004 3000.
# Assume GPR 5 contains 0x0000 0002.
# Assume GPR 6 contains 0xFFFF FFFF.
rlwnm. 6,4,5,0,0x1D
# GPR 6 now contains 0xC010 C000.
# CRF 0 now contains 0x8.
# Under the same conditions
#  rlwnm. 6,4,5,0xFFFFFFFC
# will produce the same result.

Related Information

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .