Computes the most significant 32 bits of the 64-bit product of two 32-bit integers.
Note: The mulhw instruction is supported only in the PowerPC architecture.
The mulhw instruction multiplies the contents of general-purpose register (GPR) RA and GPR RB and places the most significant 32 bits of the 64-bit product in the target GPR RT. Both the operands and the product are interpreted as signed integers.
The mulhw instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.
|Syntax Form||Record Bit (Rc)||Condition Register Field 0|
If the syntax form sets the Record (Rc) bit to 1, then the Less Than (LT) zero, Greater Than (GT) zero and Equal To (EQ) zero bits in Condition Register Field 0 reflect the result placed in GPR RT, and the Summary Overflow (SO) bit is copied from the XER to the SO bit in Condition Register Field 0.
|RT||Specifies target general-purpose register where the result of operation is stored.|
|RA||Specifies source general-purpose register for EA calculation.|
|RB||Specifies source general-purpose register for EA calculation.|
# Assume GPR 4 contains 0x0000 0003. # Assume GPR 10 contains 0x0000 0002. mulhw 6,4,10 # GPR 6 now contains 0x0000 0000.
# Assume GPR 4 contains 0x0000 4500. # Assume GPR 10 contains 0x8000 7000. # Assume XER(SO) = 0. mulhw. 6,4,10 # GPR 6 now contains 0xFFFF DD80. # Condition Register Field 0 now contains 0x4.
The mul (Multiply) instruction, mulhwu (Multiply High Word Unsigned) instruction, mulli or muli (Multiply Low Immediate) instruction, mullw or muls (Multiply Low Word) instruction.
Fixed-Point Arithmetic Instructions.