mul (Multiply) Instruction

Purpose

Multiplies the contents of two general-purpose registers and stores the result in a third general-purpose register.

Note: The mul instruction is supported only in the POWER architecture.

Syntax

Description

The mul instruction multiplies the contents of general-purpose register (GPR) RA and GPR RB, and stores bits 0-31 of the result in the target GPR RT and bits 32-63 of the result in the MQ Register.

The mul instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The four syntax forms of the mul instruction never affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction sets the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register to 1 if the product is greater than 32 bits. If the syntax form sets the Record (Rc) bit to 1, then the Less Than (LT) zero, Greater Than (GT) zero and Equal To (EQ) zero bits in Condition Register Field 0 reflect the result in the low-order 32 bits of the MQ Register.

Parameters

Examples

1. The following code multiplies the contents of GPR 4 by the contents of GPR 10 and stores the result in GPR 6 and the MQ Register:

   # Assume GPR 4 contains 0x0000 0003.
   # Assume GPR 10 contains 0x0000 0002.
   mul 6,4,10
   # MQ Register now contains 0x0000 0006.
   # GPR 6 now contains 0x0000 0000.

2. The following code multiplies the contents of GPR 4 by the contents of GPR 10, stores the result in GPR 6 and the MQ Register, and sets Condition Register Field 0 to reflect the result of the operation:

   # Assume GPR 4 contains 0x0000 4500.
   # Assume GPR 10 contains 0x8000 7000.
   mul. 6,4,10
   # MQ Register now contains 0x1E30 0000.
   # GPR 6 now contains 0xFFFF DD80.
   # Condition Register Field 0 now contains 0x4.

3. The following code multiplies the contents of GPR 4 by the contents of GPR 10, stores the result in GPR 6 and the MQ Register, and sets the Summary Overflow and Overflow bits in the Fixed-Point Exception Register to reflect the result of the operation:

   # Assume GPR 4 contains 0x0000 4500.
   # Assume GPR 10 contains 0x8000 7000.
   # Assume XER = 0.
   mulo 6,4,10
   # MQ Register now contains 0x1E30 0000.
   # GPR 6 now contains 0xFFFF DD80.
   # XER now contains 0xc000 0000.

4. The following code multiplies the contents of GPR 4 by the contents of GPR 10, stores the result in GPR 6 and the MQ Register, and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation:

   # Assume GPR 4 contains 0x0000 4500.
   # Assume GPR 10 contains 0x8000 7000.
   # Assume XER = 0.
   mulo. 6,4,10
   # MQ Register now contains 0x1E30 0000.
   # GPR 6 now contains 0xFFFF DD80.
   # Condition Register Field 0 now contains 0x5.
   # XER now contains 0xc000 0000.

Related Information

The mulhw (Multiply High Word) instruction, mulhwu (Multiply High Word Unsigned) instruction, mulli or muli (Multiply Low Immediate) instruction, mullw or muls (Multiply Low Word) instruction.

Fixed-Point Processor.

Fixed-Point Arithmetic Instructions.

Using Milicode Routines.