Multiply 2 unsigned 64-bit values together. Place the high-order 64 bits of the result into a register.
| PowerPC | |
|---|---|
| mulhdu | RT, RA, RB (Rc=0) |
| mulhdu. | RT, RA, RB (Rc=1) |
Both the operands and the product are interpreted as unsigned integers, except that if Rc = 1 (the mulhw. instruction) the first three bits of the condition register 0 field are set by signed comparison of the result to zero.
The 64-bit operands are the contents of RA and RB. The low-order 64 bits of the 128-bit product of the operands are placed into RT.
Other registers altered:
Affected: LT, GT, EQ, SO (if Rc = 1)
Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 64-bit result.
This instruction may execute faster on some implementations if RB contains the operand having the smaller absolute value.
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.