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AIX Version 4.3 Assembler Language Reference

mullw or muls (Multiply Low Word) Instruction

Purpose

Computes the least significant 32 bits of the 64-bit product of two 32-bit integers.

Syntax

PowerPC
mullw RT,RA,RB
mullw. RT,RA,RB
mullwo RT,RA,RB
mullwo. RT,RA,RB
POWER
muls RT,RA,RB
muls. RT,RA,RB
mulso RT,RA,RB
mulso. RT,RA,RB

Description

The mullw and muls instructions multiply the contents of general-purpose register (GPR) RA by the contents of GPR RB, and place the least significant 32 bits of the result in the target GPR RT.

The mullw instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The muls instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

Syntax Form Overflow Exception (OE) Fixed-Point Exception Register Record Bit (Rc) Condition Register Field 0
mullw 0 None 0 None
mullw. 0 None 1 LT,GT,EQ
mullwo 1 SO,OV 0 None
mullwo. 1 SO,OV 1 LT,GT,EQ
muls 0 None 0 None
muls. 0 None 1 LT,GT,EQ
mulso 1 SO,OV 0 None
mulso. 1 SO,OV 1 LT,GT,EQ

The four syntax forms of the mullw instruction, and the four syntax forms of the muls instruction, never affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction sets the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register to 1 if the result is too large to be represented in 32 bits. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RT Specifies target general-purpose register where result of operation is stored.
RA Specifies source general-purpose register for operation.
RB Specifies source general-purpose register for operation.

Examples

  1. The following code multiplies the contents of GPR 4 by the contents of GPR 10 and stores the result in GPR 6: 
    # Assume GPR 4 holds 0x0000 3000.
# Assume GPR 10 holds 0x0000 7000.
mullw 6,4,10
# GPR 6 now holds 0x1500 0000.
  2. The following code multiplies the contents of GPR 4 by the contents of GPR 10, stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation: 
    # Assume GPR 4 holds 0x0000 4500.
# Assume GPR 10 holds 0x0000 7000.
# Assume XER(SO) = 0.
mullw. 6,4,10
# GPR 6 now holds 0x1E30 0000.
# Condition Register Field 0 now contains 0x4.
  3. The following code multiplies the contents of GPR 4 by the contents of GPR 10, stores the result in GPR 6, and sets the Summary Overflow and Overflow bits in the Fixed-Point Exception Register to reflect the result of the operation: 
    # Assume GPR 4 holds 0x0000 4500.
# Assume GPR 10 holds 0x0007 0000.
# Assume XER = 0.
mullwo 6,4,10
# GPR 6 now holds 0xE300 0000.
# XER now contains 0xc000 0000
  4. The following code multiplies the contents of GPR 4 by the contents of GPR 10, stores the result in GPR 6, and sets the Summary Overflow, Overflow, and Carry bits in the Fixed-Point Exception Register and Condition Register Field 0 to reflect the result of the operation: 
    # Assume GPR 4 holds 0x0000 4500.
# Assume GPR 10 holds 0x7FFF FFFF.
# Assume XER = 0.
mullwo. 6,4,10
# GPR 6 now holds 0xFFFF BB00.
# XER now contains 0xc000 0000
# Condition Register Field 0 now contains 0x9.

Related Information

The mul (Multiply) instruction, mulhw (Multiply High Word) instruction, mulhwu (Multiply High Word Unsigned) instruction, mulli or muli (Multiply Low Immediate) instruction.

Fixed-Point Processor.

Fixed-Point Arithmetic Instructions.

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