The AIX Version 4 assembler provides the features of the Version 3.2 assembler, and also provides the following additional features, which were introduced in AIX Version 3.2.5:
The following list is a summary of differences between the AIX Version 3.2.5 assembler and the AIX Version 4 assembler:
The following list is a summary of enhancements in the AIX Version 4.3 assembler:
The assembler supports the following systems:
The assembler also supports development of programs for the PowerPC 603 RISC Microprocessor (PowerPC Architecture).
Attention: The PowerPC 601 RISC Microprocessor implements the PowerPC architecture plus most of the POWER instructions that are not included in the PowerPC architecture. This implementation provides a POWER-to-PowerPC bridge processor that runs existing POWER applications without recompiling and also runs new PowerPC applications. Future PowerPC systems will not provide this bridge. An application should not be coded using a mixture of POWER and PowerPC architecture-unique instructions. Doing so can result in an application that will run only on a PowerPC 601 RISC Microprocessor-based system. Such an application will not run on an existing POWER machine and is unlikely to run with acceptable performance on future PowerPC machines.
There are several categories of instructions. The following table lists the categories of instructions and shows which implementations support each instruction category. The "X" means the implementation supports the instruction category.
|Implementations Supporting Each Category of Instructions|
|POWER2 and PowerPC common instructions, not in POWER||X||X||X||X||X|
|POWER-unique instructions not supported by PowerPC 601 RISC Microprocessor||X||X|
|POWER-unique instructions supported by PowerPC 601 RISC Microprocessor||X||X||X|
|POWER and PowerPC common instructions with same mnemonics||X||X||X||X||X||X|
|POWER and PowerPC common instructions with different mnemonics||X||X||X||X||X||X|
|PowerPC instructions supported by PowerPC 601 RISC Microprocessor||X||X||X|
|Instructions unique to PowerPC 601 RISC Microprocessor||X|
|PowerPC instructions not supported by PowerPC 601 RISC Microprocessor||X||X|
|PowerPC 32-bit optional instruction set 1||X||X||X|
|PowerPC 32-bit optional instruction set 2||X||X|
|Instructions unique to PowerPC 603 RISC Microprocessor||X|
The following abbreviations are used in the heading of the previous table:
|601||PowerPC 601 RISC Microprocessor|
|603||PowerPC 603 RISC Microprocessor|
|604||PowerPC 604 RISC Microprocessor|
The host machine is the hardware platform on which the assembler runs. The target machine is the platform on which the object code is run. The assembler can assemble a source program for any target machine, regardless of the host machine on which the assembler runs.
The target machine can be specified by using either the assembly mode option flag -m of the as command or the .machine pseudo-op. If neither the -m flag nor the .machine pseudo-op is used, the default assembly mode is used. If both the -m flag and a .machine pseudo-op are used, the .machine pseudo-op overrides the -m flag. Multiple .machine pseudo-ops are allowed in a source program. The value in a later .machine pseudo-op overrides a previous .machine pseudo-op.
The default assembly mode provided by the AIX Version 4 assembler, but not by the AIX Version 3.2.5 assembler, has the POWER/PowerPC intersection as the target environment, but treats all POWER/PowerPC incompatibility errors (including instructions outside the POWER/PowerPC intersection and invalid form errors) as instructional warnings. The -W and -w assembler flags control whether these warnings are displayed. In addition to being closen by the absence of the -m flag of the as command or the .machine pseudo-op, the default assembly mode can also be explicitly specified with the -m flag of the as command or with the .machine pseudo-op.
To assemble a source program containing platform-unique instructions from more than one platform without errors or warnings, use one of the following methods:
For example, the source code cannot contain both POWER-unique instructions and PowerPC 601 RISC Microprocessor-unique instructions. This is also true for each of the sub-source programs contained in a single source program. A sub-source program begins with a .machine pseudo-op and ends before the next .machine pseudo-op. Since a source program can contain multiple .machine pseudo-ops, it normally consists of several sub-source programs. For more information, see the .machine pseudo-op.
The PowerPC architecture introduces new mnemonics for instructions in the POWER architecture. The assembler supports both new (PowerPC) and existing (POWER) mnemonics. The assembler listing has a cross-reference for both mnemonics. The cross-reference is restricted to instructions that have different mnemonics in the POWER and PowerPC architectures, but which share the same op codes, functions, and operand input formats.
The assembler listing contains one new column to display mnemonics cross-reference information. For more information on the assembler listing, see "Interpreting an Assembler Listing".
The mnemonics cross-reference helps the user migrate a source program from one architecture to another. The new -s flag for the as command provides a mnemonics cross-reference in the assembler listing to assist with migration. If the -s flag is not used, no mnemonics cross-reference is provided.
During the assembly process the assembler determines which instruction set (from a list of several complete instruction sets defined in the architectures or processor implementations) is the smallest instruction set containing all the instructions used in the program. The program is given a CPU ID value indicating this instruction set. Therefore a CPU ID indicates the target environment on which the object code can be run. The CPU ID value for the program is an assembler output value included in the XCOFF object file generated by the assembler.
CPU ID can have the following values:
|com||All instructions used in the program are in the PowerPC and POWER architecture intersection. (The com instruction set is the smallest instruction set.)|
|ppc||All instructions used in the program are in the PowerPC architecture, 32-bit mode, but the program does not satisfy the conditions for CPU ID value com. (The ppc instruction set is a superset of the com instruction set.)|
|pwr||All instructions used in the program are in the POWER architecture, POWER implementation, but the program does not satisfy the conditions for CPU ID value com. (The pwr instruction set is a superset of the com instruction set.)|
|pwr2||All instructions used in the program are in the POWER architecture, POWER2 implementation, but the program does not satisfy the conditions for CPU ID values com, ppc, or pwr. (The pwr2 instruction set is a superset of the pwr instruction set.)|
|any||The program contains a mixture of instructions from the valid architectures or implementations, or contains implementation-unique instructions.The program does not satisfy the conditions for CPU ID values com, ppc, pwr, or pwr2. (The any instruction set is the largest instruction set.)|
The assembler output value CPU ID is not the same thing as the assembly mode. The assembly mode (determined by the -m flag of the as command and by use of the .machine pseudo-op in the program) determines which instructions the assembler accepts without errors or warnings. The CPU ID is an output value indicating which instructions are actually used.
In the output XCOFF file, the CPU ID is stored in the low-order byte of the n_type field in a symbol table entry with the C_FILE storage class. The following list shows the low-order byte values and corresponding CPU IDs for AIX Version 4:
|Low-Order Byte||CPU ID|
|0||Not a defined value. An invalid value or object was assembled prior to definition of the CPU-ID field.|
For cascade compilers, the assembler records the source-language type. In the XCOFF file, the high-order byte of the n_type field of a symbol table entry with the C_FILE storage class holds the source language type information. The following language types are defined:
The source language type is indicated by the .source pseudo-op. By default, the source-language type is "Assembler." For more information, see the .source pseudo-op.
Messages 145 through 173, see "Appendix A. Messages", were added to the assembler in AIX Version 3.2.5. These messages report the following error conditions:
Some fields are defined with more than one / (slash) (for example, "/// "). If they are coded as nonzero, the form is invalid. If certain input operands are used for these fields, they must be checked. For this reason, the following two instructions are checked:
Note: The svc and svcl instructions are not supported in PowerPC target modes. The svcla instruction is supported only on the PowerPC 601 RISC Microprocessor.
The encoding for the BO field is defined in the section "Branch Processor Instructions" of PowerPC Architecture. The following list gives brief descriptions of the possible values for this field:
|0000y||Decrement the Count Register (CTR); then branch if the value of the decremented CTR is not equal to 0 and the condition is False.|
|0001y||Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is False.|
|001zy||Branch if the condition is False.|
|0100y||Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is True.|
|0101y||Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0 and the condition is True.|
|011zy||Branch if the condition is True.|
|1z00y||Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0.|
|1z01y||Decrement the CTR; then branch if the value of the decremented CTR is not equal to 0.|
|1z1zz|| Branch always.
The z bit denotes a bit that must be 0. If the bit is not 0, the instruction form is invalid.
Note: The y bit provides a hint about whether a conditional branch is likely to be taken. The value of this bit can be either 0 or 1. The default value is 0. The extended mnemonics for Branch Prediction as defined in PowerPC Architecture are used to set this bit to 0 or 1. Support for extended mnemonics for branch prediction is new in AIX Version 4. (See "Extended Mnemonics for Branch Prediction" for more information.)
Branch always instructions do not have a y bit in the BO field. Bit 4 of the BO field should contain 0. Otherwise, the instruction form is invalid.
The third bit of the BO field is specified as the "decrement and test CTR" option. For Branch Conditional to Count Register instructions, the third bit of the BO field must not be 0. Otherwise, the instruction form is invalid and error 163 is reported.
This restriction applies to the following instructions:
Note: If the target mode is com, or ppc, the assembler checks the update form of fixed-point load instructions, update form of fixed-point store instructions, update form of floating-point load and store instructions, multiple-register load instructions, and fixed-point compare instructions, and reports any errors. If the target mode is any, pwr, pwr2, or 601, no check is performed.
Warning messages are listed when the -w flag is used with the as command. Some warning messages are related to instructions with the same op code for POWER and PowerPC:
|Same Op Codes with Different Mnemonics|
See "Incompatibilities with the POWER Architecture" in the appendix of PowerPC Architecture for more information about these instruction functions in the PowerPC architecture as well as the differences between the POWER and PowerPC architectures.
TID, MQ, SDR0, RTCU, and RTCL are special-purpose registers (SPRs) defined in the POWER architecture. They are not valid in the PowerPC architecture. However, MQ, RTCU, and RTCL are still available in the PowerPC 601 RISC Microprocessor.
DBATL, DBATU, IBATL, IBATU, TBL, and TBU are SPRs defined in the PowerPC architecture. They are not supported for the PowerPC 601 RISC Microprocessor. The PowerPC 601 RISC Microprocessor uses the BATL and BATU SPRs instead.
The assembler provides the extended mnemonics for "move to or from SPR" instructions. The extended mnemonics include all the SPRs defined in the POWER and PowerPC architectures. An error is generated if an invalid extended mnemonic is used. The assembler does not support extended mnemonics for any of the following:
The assembler does not check the SPR field's encoding value for the mtspr and mfspr instructions, because the SPR encoding codes could be changed or reused. However, the assembler does check the SPR field's value range. If the target mode is pwr, pwr2, or com, the SPR field has a 5-bit length and a maximum value of 31. Otherwise, the SPR field has a 10-bit length and a maximum value of 1023.
To maintain source-code compatibility of the POWER and PowerPC architectures, the assembler assumes that the low-order 5 bits and high-order 5 bits of the SPR number are reversed before they are used as the input operands to the mfspr or mtspr instruction.
AIX Assembler Overview.
Features of the Assembler Prior to AIX Version 3.2.5.
Overview of Assembling and Linking a Program.
The as command.
The .machine pseudo-op, .source pseudo-op.