Extended Mnemonics of Branch Instructions

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AIX Version 4.3 Assembler Language Reference

Extended Mnemonics of Branch Instructions

The assembler supports extended mnemonics for Branch Conditional, Branch Conditional to Link Register, and Branch Conditional to Count Register instructions. Since the base mnemonics for all the Branch Conditional instructions are in the com assembly mode, all of their extended mnemonics are also in the com assembly mode.

Note: Support for extended mnemonics for branch prediction is new in the AIX Version 4 assembler.

Extended mnemonics are constructed by incorporating the BO and BI input operand into the mnemonics.

Branch Mnemonics That Incorporate Only the BO Operand

The following tables show the instruction format for extended mnemonics that incorporate only the BO field. The target address is specified by the target_addr operand. The bit in the condition register for condition comparison is specified by the BI operand. The value of the BI operand can be specified by an expression. The CR field number should be multiplied by four to get the correct CR bit, since each CR field has four bits.

Note: Some extended mnemonics have two input operand formats.

POWER Extended Mnemonics (BO Field Only)
Mnemonics	Input Operands	Equivalent to
bdz, bdza, bdzl, bdzla	target_addr	bc, bca, bcl, bcla	18, 0, target_addr
bdn, bdna, bdnl, bdnla	target_addr	bc, bca, bcl, bcla	16, 0, target_addr
bdzr, bdzrl	None	bcr, bcrl	18, 0
bdnr, bdnrl	None	bcr, bcrl	16, 0
bbt, bbta, bbtl, bbtla	1) BI, target_addr	bc, bca, bcl, bcla	12, BI, target_addr
	2) target_addr		12, 0, target_addr
bbf, bbfa, bbfl, bbfla	1) BI, target_addr	bc, bca, bcl, bcla	4, BI, target_addr
	2) target_addr		4, 0, target_addr
bbtr, bbtc, bbtrl, bbtcl	1) BI	bcr, bcc, bcrl, bccl	12, BI
	2) None		12, 0
bbfr, bbfc, bbfrl, bbfcl	1) BI	bcr, bcc, bcrl, bccl	4, BI
	2) None		4, 0
br, bctr, brl, bctrl	None	bcr, bcc, bcrl, bccl	20, 0

PowerPC Extended Mnemonics (BO Field Only)
Mnemonics	Input Operands	Equivalent to
bdz, bdza, bdzl, bdzla	target_addr	bc, bca, bcl, bcla 18, 0, target_addr
bdnz, bdnza, bdnzl, bdnzla	target_addr	bc, bca, bcl, bcla 16, 0, target_addr
bdzlr, bdzlrl	None	bclr, bclrl 18, 0
bdnzlr, bdnzlrl	None	bclr, bclrl 16, 0
bt, bta, btl, btla	1) BI, target_addr	bc, bca, bcl, bcla 12, BI, target_addr
	2) target_addr	12, 0, target_addr
bf, bfa, bfl, bfla	1) BI, target_addr	bc, bca, bcl, bcla 4, BI, target_addr
	2) target_addr	4, 0, target_addr
bdzt, bdzta, bdztl, bdztla	1) BI, target_addr	bc, bca, bcl, bcla 10, BI, target_addr
	2) target_addr	10, 0, target_addr
bdzf, bdzfa, bdzfl, bdzfla	1) BI, target_addr	bc, bca, bcl, bcla 2, BI, target_addr
	2) target_addr	2, 0, target_addr
bdnzt, bdnzta, bdnztl, bdnztla	1) BI, target_addr	bc, bca, bcl, bcla 8, BI, target_addr
	2) target_addr	8, 0, target_addr
bdnzf, bdnzfa, bdnzfl, bdnzfla	1) BI, target_addr	bc, bca, bcl, bcla 0, BI, target_addr
	2) target_addr	0, 0, target_addr
btlr, btctr, btlrl, btctrl	1) BI	bclr, bcctr, bclrl, bcctrl 12, BI
	2) None	12, 0
bflr, bfctr, bflrl, bfctrl	1) BI	bclr, bcctr, bclrl, bcctrl 4, BI
	2) None	4, 0
bdztlr, bdztlrl	1) BI	bclr, bclrl 10, BI
	2) None	10, 0
bdzflr, bdzflrl	1) BI	bclr, bclrl 2, BI
	2) None	2, 0
bdnztlr, bdnztlrl	1) BI	bclr, bclrl 8, BI
	2) None	8, 0
bdnzflr, bdnzflrl	1) BI	bclr, bclrl 0, BI
	2) None	0, 0
blr, bctr, blrl, bctrl	None	bclr, bcctr, bclrl, bcctrl 20, 0

Extended Branch Mnemonics That Incorporate the BO Field and a Partial BI Field

When the BO field and a partial BI field are incorporated, the instruction format is one of the following:

mnemonic BIF, target_addr
mnemonic target_addr

where the BIF operand specifies the CR field number (0-7) and the target_addr operand specifies the target address. If CR0 is used, the BIF operand can be omitted.

Based on the bits definition in the CR field, the following set of codes has been defined for the most common combinations of branch conditions:

Branch Code	Meaning
lt	less than *
eq	equal to *
gt	greater than *
so	summary overflow *
le	less than or equal to * (not greater than)
ge	greater than or equal to * (not less than)
ne	not equal to *
ns	not summary overflow *
nl	not less than
ng	not greater than
z	zero
nu	not unordered (after floating-point comparison)
nz	not zero
un	unordered (after floating-point comparison)

The assembler supports six encoding values for the BO operand:

Branch if condition true (BO=12):
POWERPowerPC

bxx bxx

bxxa bxxa

bxxl bxxl

bxxla bxxla

bxxr bxxlr

bxxrl bxxlrl

bxxc bxxctr

bxxcl bxxctrl
where xx specifies a BI operand branch code of lt , gt , eq , so , z , or un .
Branch if condition false (BO=04):
POWERPowerPC

bxx bxx

bxxa bxxa

bxxl bxxl

bxxla bxxla

bxxr bxxlr

bxxrl bxxlrl

bxxc bxxctr

bxxcl bxxctrl
where xx specifies a BI operand branch code of ge , le , ne , ns , nl , ng , nz , or nu .
Decrement CTR, then branch if CTR is nonzero and condition is true (BO=08):
- bdnxx
where xx specifies a BI operand branch code of lt , gt , eq , or so (marked by an * (asterisk) in the Branch Code list).
Decrement CTR, then branch if CTR is nonzero and condition is false (BO=00):
- bdnxx
where xx specifies a BI operand branch code of le , ge , ne , or ns (marked by an * (asterisk) in the Branch Code list).
Decrement CTR, then branch if CTR is zero and condition is true (BO=10):
- bdzxx
where xx specifies a BI operand branch code of lt , gt , eq , or so (marked by an * (asterisk) in the Branch Code list).
Decrement CTR, then branch if CTR is zero and condition is false (BO=02):
- bdzxx
where xx specifies a BI operand branch code of le , ge , ne , or ns (marked by an * (asterisk) in the Branch Code list).

POWERPowerPC
bxx	bxx
bxxa	bxxa
bxxl	bxxl
bxxla	bxxla
bxxr	bxxlr
bxxrl	bxxlrl
bxxc	bxxctr
bxxcl	bxxctrl

POWERPowerPC
bxx	bxx
bxxa	bxxa
bxxl	bxxl
bxxla	bxxla
bxxr	bxxlr
bxxrl	bxxlrl
bxxc	bxxctr
bxxcl	bxxctrl

BI Operand of Branch Conditional Instructions for Basic and Extended Mnemonics

The BI operand specifies a bit (0:31) in the Condition Register for condition comparison. The bit is set by a compare instruction. The bits in the Condition Register are grouped into eight 4-bit fields. These fields are named CR field 0 through CR field 7 (CR0...CR7). The bits of each field are interpreted as follows:

Bit	Description
0	Less than; floating-point less than
1	Greater than; floating-point greater than
2	Equal; floating-point equal
3	Summary overflow; floating-point unordered

Normally the symbols shown in the BI Operand Symbols for Basic and Extended Branch Conditional Mnemonics table are defined for use in BI operands. The assembler supports expressions for the BI operands. The expression is a combination of values and the following symbols.

BI Operand Symbols for Basic and Extended Branch Conditional Mnemonics
Symbol	Value	Meaning
lt	0	less than
gt	1	greater than
eq	2	equal
so	3	summary overflow
un	3	unordered (after floating-point comparison)
cr0	0	CR field 0
cr1	1	CR field 1
cr2	2	CR field 2
cr3	3	CR field 3
cr4	4	CR field 4
cr5	5	CR field 5
cr6	6	CR field 6
cr7	7	CR field 7

When using an expression for the BI field in the basic or extended mnemonics with only the BO field incorporated, the CR field number should be multiplied by 4 to get the correct CR bit, since each CR field has four bits.

To decrement CTR, then branch only if CTR is not zero and condition in CR5 is equal:
```
bdnzt   4*cr5+eq, target_addr
```
This is equivalent to:
```
bc   8, 22, target_addr
```
To decrement CTR, then branch only if CTR is not zero and condition in CR0 is equal:
```
bdnzt   eq, target_addr
```
This is equivalent to:
```
bc   8, 2, target_addr
```
If the BI operand specifies Bit 0 of CR0, the BI operand can be omitted.
To decrement CTR, then branch only if CTR is zero:
```
bdz   target_addr
```
This is equivalent to:
```
bc   18, 0, target_addr
```

For extended mnemonics with the BO field and a partial BI field incorporated, the value of the BI operand indicates the CR field number. Valid values are 0-7. If a value of 0 is used, the BI operand can be omitted.

To branch if CR0 reflects a condition of not less than:
```
bge   target_addr
```
This is equivalent to:
```
bc   4, 0, target_addr
```
To branch to an absolute target if CR4 indicates greater than, and set the Link register:
```
bgtla   cr4, target_addr
```
This is equivalent to:
```
bcla   12, 17, target_addr
```
The BI operand CR4 is internally expanded to 16 by the assembler. After the gt (greater than) is incorporated, the result of the BI field is 17.

Extended Mnemonics for Branch Prediction

If the likely outcome (branch or fall through) of a given Branch Conditional instruction is known, the programmer can include this information in the assembler source program by adding a branch prediction suffix to the mnemonic of the instruction. The assembler uses the branch prediction information to determine the value of a bit in the machine instruction. Using a branch prediction suffix may improve the average performance of a Branch Conditional instruction.

The following suffixes can be added to any Branch Conditional mnemonic, either basic or extended:

+	Predict branch to be taken
-	Predict branch not to be taken (fall through)

The branch prediction suffix should be placed immediately after the rest of the mnemonic (with no separator character). A separator character (space or tab) should be used between the branch prediction suffix and the operands.

If no branch prediction suffix is included in the mnemonic, the assembler uses the following default assumptions in constructing the machine instruction:

For relative or absolute branches ( bc[l][a]) with negative displacement fields, the branch is predicted to be taken.
For relative or absolute branches ( bc[l][a]) with nonnegative displacement fields, the branch is predicted not to be taken (fall through predicted).
For branches to an address in the LR or CTR (bclr[l]) or (bcctr[l]), the branch is predicted not to be taken (fall through predicted).

The portion of the machine instruction which is controlled by the branch prediction suffix is the y bit of the BO field. The y bit is set as follows:

Specifying no branch prediction suffix, or using the suffix which is the same as the default assumption causes the y bit to be set to 0.
Specifying a branch prediction suffix which is the opposite of the default assumption causes the y bit to be set to 1.

The following examples illustrate use of branch prediction suffixes:

Branch if CR0 reflects condition less than. Executing the instruction will usually result in branching.
```
blt+  target
```
Branch if CRO reflects condition less than. Target address is in the Link Register. Executing the instruction will usually result in falling through to the next instruction.
```
bltlr-
```

The following is a complete list of all the Branch Prediction instructions that are supported by the assembler in AIX Version 4:

       bc+             bc-             bca+            bca-
       bcctr+          bcctr-          bcctrl+         bcctrl-
       bcl+            bcl-            bcla+           bcla-
       bclr+           bclr-           bclrl+          bclrl-
       bdneq+          bdneq-          bdnge+          bdnge-
       bdngt+          bdngt-          bdnle+          bdnle-
       bdnlt+          bdnlt-          bdnne+          bdnne-
       bdnns+          bdnns-          bdnso+          bdnso-
       bdnz+           bdnz-           bdnza+          bdnza-
       bdnzf+          bdnzf-          bdnzfa+         bdnzfa-
       bdnzfl+         bdnzfl-         bdnzfla+        bdnzfla-
       bdnzflr+        bdnzflr-        bdnzflrl+       bdnzflrl-
       bdnzl+          bdnzl-          bdnzla+         bdnzla-
       bdnzlr+         bdnzlr-         bdnzlrl+        bdnzlrl-
       bdnzt+          bdnzt-          bdnzta+         bdnzta-
       bdnztl+         bdnztl-         bdnztla+        bdnztla-
       bdnztlr+        bdnztlr-        bdnztlrl+       bdnztlrl-
       bdz+            bdz-            bdza+           bdza-
       bdzeq+          bdzeq-          bdzf+           bdzf-
       bdzfa+          bdzfa-          bdzfl+          bdzfl-
       bdzfla+         bdzfla-         bdzflr+         bdzflr-
       bdzflrl+        bdzflrl-        bdzge+          bdzge-
       bdzgt+          bdzgt-          bdzl+           bdzl-
       bdzla+          bdzla-          bdzle+          bdzle-
       bdzlr+          bdzlr-          bdzlrl+         bdzlrl-
       bdzlt+          bdzlt-          bdzne+          bdzne-
       bdzns+          bdzns-          bdzso+          bdzso-
       bdzt+           bdzt-           bdzta+          bdzta-
       bdztl+          bdztl-          bdztla+         bdztla-
       bdztlr+         bdztlr-         bdztlrl+        bdztlrl-
       beq+            beq-            beqa+           beqa-
       beqctr+         beqctr-         beqctrl+        beqctrl-
       beql+           beql-           beqla+          beqla-
       beqlr+          beqlr-          beqlrl+         beqlrl-
       bf+             bf-             bfa+            bfa-
       bfctr+          bfctr-          bfctrl+         bfctrl-
       bfl+            bfl-            bfla+           bfla-
       bflr+           bflr-           bflrl+          bflrl-
       bge+            bge-            bgea+           bgea-
       bgectr+         bgectr-         bgectrl+        bgectrl-
       bgel+           bgel-           bgela+          bgela-
       bgelr+          bgelr-          bgelrl+         bgelrl-
       bgt+            bgt-            bgta+           bgta-
       bgtctr+         bgtctr-         bgtctrl+        bgtctrl-
       bgtl+           bgtl-           bgtla+          bgtla-
       bgtlr+          bgtlr-          bgtlrl+         bgtlrl-
       ble+            ble-            blea+           blea-
       blectr+         blectr-         blectrl+        blectrl-
       blel+           blel-           blela+          blela-
       blelr+          blelr-          blelrl+         blelrl-
       blt+            blt-            blta+           blta-
       bltctr+         bltctr-         bltctrl+        bltctrl-
       bltl+           bltl-           bltla+          bltla-
       bltlr+          bltlr-          bltlrl+         bltlrl-
       bne+            bne-            bnea+           bnea-
       bnectr+         bnectr-         bnectrl+        bnectrl-
       bnel+           bnel-           bnela+          bnela-
       bnelr+          bnelr-          bnelrl+         bnelrl-
       bng+            bng-            bnga+           bnga-
       bngctr+         bngctr-         bngctrl+        bngctrl-
       bngl+           bngl-           bngla+          bngla-
       bnglr+          bnglr-          bnglrl+         bnglrl-
       bnl+            bnl-            bnla+           bnla-
       bnlctr+         bnlctr-         bnlctrl+        bnlctrl-
       bnll+           bnll-           bnlla+          bnlla-
       bnllr+          bnllr-          bnllrl+         bnllrl-
       bns+            bns-            bnsa+           bnsa-
       bnsctr+         bnsctr-         bnsctrl+        bnsctrl-
       bnsl+           bnsl-           bnsla+          bnsla-
       bnslr+          bnslr-          bnslrl+         bnslrl-
       bnu+            bnu-            bnua+           bnua-
       bnuctr+         bnuctr-         bnuctrl+        bnuctrl-
       bnul+           bnul-           bnula+          bnula-
       bnulr+          bnulr-          bnulrl+         bnulrl-
       bnz+            bnz-            bnza+           bnza-
       bnzctr+         bnzctr-         bnzctrl+        bnzctrl-
       bnzl+           bnzl-           bnzla+          bnzla-
       bnzlr+          bnzlr-          bnzlrl+         bnzlrl-
       bso+            bso-            bsoa+           bsoa-
       bsoctr+         bsoctr-         bsoctrl+        bsoctrl-
       bsol+           bsol-           bsola+          bsola-
       bsolr+          bsolr-          bsolrl+         bsolrl-
       bt+             bt-             bta+            bta-
       btctr+          btctr-          btctrl+         btctrl-
       btl+            btl-            btla+           btla-
       btlr+           btlr-           btlrl+          btlrl-
       bun+            bun-            buna+           buna-
       bunctr+         bunctr-         bunctrl+        bunctrl-
       bunl+           bunl-           bunla+          bunla-
       bunlr+          bunlr-          bunlrl+         bunlrl-
       bz+             bz-             bza+            bza-
       bzctr+          bzctr-          bzctrl+         bzctrl-
       bzl+            bzl-            bzla+           bzla-
       bzlr+           bzlr-           bzlrl+          bzlrl-

Related Information

Extended Instruction Mnemonics Overview.

Extended Mnemonics of Condition Register Logical Instructions.

Extended Mnemonics of Fixed-Point Arithmetic Instructions.

Extended Mnemonics of Fixed-Point Compare Instructions.

Extended Mnemonics of Fixed-Point Load Instructions.

Extended Mnemonics of Fixed-Point Logical Instructions.

Extended Mnemonics of Fixed-Point Trap Instructions.

Extended Mnemonics of Moving from or to Special-Purpose Registers.

Extended Mnemonics of Fixed-Point Rotate and Shift Instructions.

The bc (Branch Conditional) instruction, bclr or bcr (Branch Conditional Link Register) instruction, bcctr or bcc (Branch Conditional to Count Register) instruction.

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