Generates a supervisor call interrupt.
Note: The svc instruction is supported only in the POWER architecture.
The svc instruction generates a supervisor call interrupt and places bits 16-31 of the svc instruction into bits 0-15 of the Count Register (CR) and bits 16-31 of the Machine State Register (MSR) into bits 16-31 of the CR.
Consider the following when using the svc instruction:
- To ensure correct operation, an svc instruction must be preceded by an unconditional branch or a CR instruction. If a useful instruction cannot be scheduled as specified, use a no-op version of the cror instruction with the following syntax:
- The svc instruction has the same op code as the sc (System Call) instruction.
The svc instruction has four syntax forms. Each syntax form affects the MSR.
|Syntax Form||Link Bit (LK)||SVC Absolute Bit (SA)||Machine State Register Bits|
|svc||0||0||EE,PR,FE set to zero|
|svcl||1||0||EE,PR,FE set to zero|
|svca||0||1||EE,PR,FE set to zero|
|svcla||1||1||EE,PR,FE set to zero|
The four syntax forms of the svc instruction never affect the FP, ME, AL, IP, IR, or DR bits of the MSR. The EE, PR, and FE bits of the MSR are always set to 0. The Fixed-Point Exception Register and Condition Register Field 0 are unaffected by the svc instruction.
|LEV||Specifies execution address.|
|FL1||Specifies field for optional data passing to SVC routine.|
|FL2||Specifies field for optional data passing to SVC routine.|
|SV||Specifies field for optional data passing to SVC routine.|
The cror (Condition Register OR) instruction, sc (System Call) instruction.
System Call Instructions.
Functional Differences for POWER and PowerPC Instructions.