Conditionally branches to a specified target address.
See "Extended Mnemonics of Branch Instructions" for more information.
The bc instruction branches to an instruction specified by the branch target address. The branch target address is computed one of two ways:
The bc instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.
|Syntax Form||Absolute Address Bit (AA)||Fixed-Point Exception Register||Link Bit (LK)||Condition Register Field 0|
The four syntax forms of the bc instruction never affect the Fixed-Point Exception Register or Condition Register Field 0. The syntax forms set the AA bit and the Link bit (LK) and determine which method of calculating the branch target address is used. If the Link Bit (LK) is set to 1, then the effective address of the instruction is placed in the Link Register.
The Branch Option field (BO) is used to combine different types of branches into a single instruction. Extended mnemonics are provided to set the Branch Option field automatically.
The encoding for the BO field is defined in PowerPC Architecture. The following list gives brief descriptions of the possible values for this field:
|0000y||Decrement the CTR; then branch if the decremented CTR is not 0 and the condition is False.|
|0001y||Decrement the CTR; then branch if the decremented CTR is 0 and the condition is False.|
|001zy||Branch if the condition is False.|
|0100y||Decrement the CTR; then branch if bits the decremented CTR is not 0 and the condition is True.|
|0101y||Decrement the CTR; then branch if the decremented CTR is 0 and the condition is True.|
|011zy||Branch if the condition is True.|
|1z00y||Decrement the CTR; then branch if the decremented CTR is not 0.|
|1z01y||Decrement the CTR; then branch if the decremented CTR is 0.|
In the PowerPC Architecture, the z bit denotes a bit that must be 0. If the bit is not 0, the instruction form is invalid.
In the PowerPC Architecture, the y bit provides a hint about whether a conditional branch is likely to be taken. The value of this bit can be either 0 or 1. The default value is 0.
In the POWER Architecture, the z and y bits can be either 0 or 1.
|target_address||Specifies the target address. For absolute branches such as bca and bcla, the target address can be immediate data containable in 16 bits.|
|BI||Specifies bit in Condition Register for condition comparison.|
|BO||Specifies Branch Option field used in instruction.|
The following code branches to a target address dependent on the value in the Count Register:
addi 8,0,3 # Loads GPR 8 with 0x3. mtctr 8 # The Count Register (CTR) equals 0x3. addic. 9,8,0x1 # Adds one to GPR 8 and places the result in GPR 9. # The Condition Register records a comparison against zero
# with the result. bc 0xC,0,there # Branch is taken if condition is true. 0 indicates that # the 0 bit in the Condition Register is checked to # determine if it is set (the LT bit is on). If it is set, # the branch is taken. bcl 0x8,2,there # CTR is decremented by one, becomming 2.
# The branch is taken if CTR is not equal to 0 and CTR bit 2 # is set (the EQ bit is on). # The Link Register contains address of next instruction.
AIX Assembler Overview.