Conditionally branches to the address contained within the Count Register.
See "Extended Mnemonics of Branch Instructions" for more information.
The bcctr and bcc instructions conditionally branch to an instruction specified by the branch target address contained within the Count Register. The branch target address is the concatenation of Count Register bits 0-29 and b'00'.
The bcctr and bcc instructions have two syntax forms. Each syntax form has a different effect on the Link bit and Link Register.
|Syntax Form||Absolute Address Bit (AA)||Fixed-Point Exception Register||Link Bit (LK)||Condition Register Field 0|
The two syntax forms of the bcctr and bcc instructions never affect the Fixed-Point Exception Register or Condition Register Field 0. If the Link bit is 1, then the effective address of the instruction following the branch instruction is placed into the Link Register.
The Branch Option field (BO) is used to combine different types of branches into a single instruction. Extended mnemonics are provided to set the Branch Option field automatically.
The encoding for the BO field is defined in PowerPC Architecture. The following list gives brief descriptions of the possible values for this field:
|0000y||Decrement the CTR; then branch if the decremented CTR is not 0 and the condition is False.|
|0001y||Decrement the CTR; then branch if the decremented CTR is 0 and the condition is False.|
|001zy||Branch if the condition is False.|
|0100y||Decrement the CTR; then branch if bits the decremented CTR is not 0 and the condition is True.|
|0101y||Decrement the CTR; then branch if the decremented CTR is 0 and the condition is True.|
|011zy||Branch if the condition is True.|
|1z00y||Decrement the CTR; then branch if the decremented CTR is not 0.|
|1z01y||Decrement the CTR; then branch if the decremented CTR is 0.|
In the PowerPC Architecture, the z bit denotes a bit that must be 0. If the bit is not 0, the instruction form is invalid.
In the PowerPC Architecture, the y bit provides a hint about whether a conditional branch is likely to be taken. The value of this bit can be either 0 or 1. The default value is 0.
In the POWER Architecture, the z and y bits can be either 0 or 1.
|BO||Specifies Branch Option field.|
|BI||Specifies bit in Condition Register for condition comparison.|
|BIF||Specifies the Condition Register field that specifies the Condition Register bit (LT, GT, EQ, or SO) to be used for condition comparison.|
The following code branches from a specific address, dependent on a bit in the Condition Register, to the address contained in the Count Register:
bcctr 0x4,0 cror 31,31,31 # Branch occurs if LT bit in the Condition Register is 0. # The branch will be to the address contained in # the Count Register. bcctrl 0xC,1 return: cror 31,31,31 # Branch occurs if GT bit in the Condition Register is 1. # The branch will be to the address contained in # the Count Register. # The Link register now contains the address of return.
AIX Assembler Overview.