Ensures that cache-inhibited storage accesses are performed in main memory in the order specified by the program.
Note: The eieio instruction is supported only in the PowerPC architecture.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | /// |
| 11-15 | /// |
| 16-20 | /// |
| 21-30 | 854 |
| 31 | / |
PowerPC
eieio
The eieio instruction provides an ordering function that ensures that all load and store instructions initiated prior to the eieio instruction complete in main memory before any loads or stores subsequent to the eieio instruction access memory. If the eieio instruction is omitted from a program, and the memory locations are unique, the accesses to main storage may be performed in any order.
Note: The eieio instruction is appropriate for cases where the only requirement is to control the order of storage references as seen by I/O devices. However, the sync (Synchronize) instruction provides an ordering function for all instructions.
The eieio instruction has one syntax form and does not affect Condition Register Field 0 or the Fixed-Point Exception Register.
The following code ensures that, if the memory locations are in cache-inhibited storage, the load from location AA and the store to location BB are completed in main storage before the content of location CC is fetched or the content of location DD is updated:
lwz r4,AA(r1) stw r4,BB(r1) eieio lwz r5,CC(r1) stw r5,DD(r1)
Note: If the memory locations of AA, BB, CC, and DD are not in cache-inhibited memory, the eieio instruction has no effect on the order that instructions access memory.
The sync (Synchronize) or dcs (Data Cache Synchronize) instruction.