Assembler Language Reference

subfme or sfme (Subtract from Minus One Extended) Instruction

Purpose

Adds the one's complement of a general-purpose register to -1 with carry.

Syntax

Bits	Value
0-5	31
6-10	RT
11-15	RA
16-20	///
21	OE
22-30	232
31	Rc

PowerPC
subfme	RT, RA
subfme.	RT, RA
subfmeo	RT, RA
subfmeo.	RT, RA

POWER family
sfme	RT, RA
sfme.	RT, RA
sfmeo	RT, RA
sfmeo.	RT, RA

Description

The subfme and sfme instructions add the one's complement of the contents of general-purpose register(GPR) RA, the Carry Bit of the Fixed-Point Exception Register, and x'FFFFFFFF' and place the result in the target GPR RT.

The subfme instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

The sfme instruction has four syntax forms. Each syntax form has a different effect on Condition Register Field 0 and the Fixed-Point Exception Register.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
subfme	0	CA	0	None
subfme.	0	CA	1	LT,GT,EQ,SO
subfmeo	1	SO,OV,CA	0	None
subfmeo.	1	SO,OV,CA	1	LT,GT,EQ,SO
sfme	0	CA	0	None
sfme.	0	CA	1	LT,GT,EQ,SO
sfmeo	1	SO,OV,CA	0	None
sfmeo.	1	SO,OV,CA	1	LT,GT,EQ,SO

The four syntax forms of the subfme instruction, and the four syntax forms of the sfme instruction, always affect the Carry bit (CA) in the Fixed-Point Exception Register. If the syntax form sets the Overflow Exception (OE) bit to 1, the instruction effects the Summary Overflow (SO) and Overflow (OV) bits in the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RT	Specifies target general-purpose register where result of operation is stored.
RA	Specifies source general-purpose register for operation.

Examples

The following code adds the one's complement of the contents of GPR 4, the Carry bit of the Fixed-Point Exception Register, and x'FFFFFFFF' and stores the result in GPR 6:
```
# Assume GPR 4 contains 0x9000 3000.
# Assume the Carry bit is set to one.
subfme 6,4
# GPR 6 now contains 0x6FFF CFFF.
```

The following code adds the one's complement of the contents of GPR 4, the Carry bit of the Fixed-Point Exception Register, and x'FFFFFFFF', stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0xB004 3000.
# Assume the Carry bit is set to zero.
subfme. 6,4
# GPR 6 now contains 0x4FFB CFFE.
```

The following code adds the one's complement of the contents of GPR 4, the Carry bit of the Fixed-Point Exception Register, and x'FFFFFFFF', stores the result in GPR 6, and sets the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0xEFFF FFFF.
# Assume the Carry bit is set to one.
subfmeo 6,4
# GPR 6 now contains 0x1000 0000.
```

The following code adds the one's complement of the contents of GPR 4, the Carry bit of the Fixed-Point Exception Register, and x'FFFFFFFF', stores the result in GPR 6, and sets Condition Register Field 0 and the Fixed-Point Exception Register to reflect the result of the operation:
```
# Assume GPR 4 contains 0xEFFF FFFF.
# Assume the Carry bit is set to zero.
subfmeo. 6,4
# GPR 6 now contains 0x0FFF FFFF.
```

Related Information

Fixed-Point Processor .

Fixed-Point Arithmetic Instructions .