Places the result of ANDing one Condition Register bit and the complement of a Condition Register bit in a Condition Register bit.
| Bits | Value |
|---|---|
| 0-5 | 19 |
| 6-10 | BT |
| 11-15 | BA |
| 16-20 | BB |
| 21-30 | 129 |
| 31 | / |
| crandc | BT, BA, BB |
The crandc instruction logically ANDs the Condition Register bit specified in BA and the complement of the Condition Register bit specified by BB and places the result in the target Condition Register bit specified by BT.
The crandc instruction has one syntax form and does not affect the Fixed-Point Exception Register.
| BT | Specifies target Condition Register bit where result of operation is stored. |
| BA | Specifies source Condition Register bit for operation. |
| BB | Specifies source Condition Register bit for operation. |
The following code logically ANDs Condition Register bit 0 and the complement of Condition Register bit 5 and puts the result in bit 31:
# Assume Condition Register bit 0 is 1. # Assume Condition Register bit 5 is 0. crandc 31,0,5 # Condition Register bit 31 is now 1.
Condition Register Instructions .