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AIX Version 4.3 Assembler Language Reference

rlwimi or rlimi (Rotate Left Word Immediate Then Mask Insert) Instruction


Rotates the contents of a general-purpose register to the left by a specified number of bits and stores the result in another general-purpose register under the control of a generated mask.


rlwimi RA,RS,SH,MB,ME
rlwimi. RA,RS,SH,MB,ME
rlwimi RA,RS,SH,BM
rlwimi. RA,RS,SH,BM
rlimi RA,RS,SH,MB,ME
rlimi. RA,RS,SH,MB,ME
rlimi RA,RS,SH,BM
rlimi. RA,RS,SH,BM

See "Extended Mnemonics of Fixed-Point Rotate and Shift Instructions" for more information.


The rlwimi and rlimi instructions rotate left the contents of the source general-purpose register (GPR) RS by the number of bits by the SH parameter and then store the rotated data in GPR RA under control of a 32-bit generated mask defined by the values in Mask Begin (MB) and Mask End (ME). If a mask bit is 1, the instructions place the associated bit of rotated data in GPR RA; if a mask bit is 0, the GPR RA bit remains unchanged.

Consider the following when using the rlwimi and rlimi instructions:

The BM parameter can also be used to specify the mask for these instructions. The assembler will generate the MB and ME parameters from the BM value.

The rlwimi and rlimi instructions each have two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form Overflow Exception (OE) Fixed-Point Exception Register Record Bit (Rc) Condition Register Field 0
rlwimi None None 0 None
rlwimi. None None 1 LT,GT,EQ,SO
rlimi None None 0 None
rlimi. None None 1 LT,GT,EQ,SO

The syntax forms of the rlwimi and rlimi instructions never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instructions affect the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.


RA Specifies target general-purpose register where result of operation is stored.
RS Specifies source general-purpose register for operation.
SH Specifies shift value for operation.
MB Specifies begin value of mask for operation.
ME Specifies end value of mask for operation.
BM Specifies value of 32-bit mask.


  1. The following code rotates the contents of GPR 4 to the left by 2 bits and stores the masked result in GPR 6:
    # Assume GPR 4 contains 0x9000 3000.
    # Assume GPR 6 contains 0x0000 0003.
    rlwimi 6,4,2,0,0x1D
    # GPR 6 now contains 0x4000 C003.
    # Under the same conditions
    #  rlwimi 6,4,2,0xFFFFFFFC
    # will produce the same result.
  2. The following code rotates the contents of GPR 4 to the left by 2 bits, stores the masked result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:
    # Assume GPR 4 contains 0x789A 789B.
    # Assume GPR 6 contains 0x3000 0003.
    rlwimi. 6,4,2,0,0x1A
    # GPR 6 now contains 0xE269 E263.
    # CRF 0 now contains 0x8.
    # Under the same conditions
    #  rlwimi. 6,4,2,0xFFFFFFE0
    # will produce the same result.

Related Information

Fixed-Point Processor.

Fixed-Point Rotate and Shift Instructions.

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