rlmi (Rotate Left Then Mask Insert) Instruction

Purpose

Rotates the contents of a general-purpose register to the left by the number of bits specified in another general-purpose register and stores the result in a third general-purpose register under the control of a generated mask.

Note: The rlmi instruction is supported only in the POWER architecture.

Syntax

See "Extended Mnemonics of Fixed-Point Rotate and Shift Instructions" for more information.

Description

The rlmi instruction rotates the contents of the source general-purpose register (GPR) RS to the left by the number of bits specified by bits 27-31 of GPR RB and then stores the rotated data in GPR RA under control of a 32-bit generated mask defined by the values in Mask Begin (MB) and Mask End (ME).

Consider the following when using the rlmi instruction:

• If a mask bit is 1, the instruction places the associated bit of rotated data in GPR RA; if a mask bit is 0, the GPR RA bit remains unchanged.
• If the MB value is less than the ME value + 1, then the mask bits between and including the starting point and the end point are set to ones. All other bits are set to zeros.
• If the MB value is the same as the ME value + 1, then all 32 mask bits are set to ones.
• If the MB value is greater than the ME value + 1, then all of the mask bits between and including the ME value +1 and the MB value -1 are set to zeros. All other bits are set to ones.

The parameter BM can also be used to specify the mask for this instruction. The assembler will generate the MB and ME parameters from BM.

The rlmi instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

The two syntax forms of the rlmi instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

Examples

1. The following code rotates the contents of GPR 4 by the value contained in bits 27-31 in GPR 5 and stores the masked result in GPR 6:

   # Assume GPR 4 contains 0x9000 3000.
   # Assume GPR 5 contains 0x0000 0002.
   # Assume GPR 6 contains 0xFFFF FFFF.
   rlmi 6,4,5,0,0x1D
   # GPR 6 now contains 0x4000 C003.
   # Under the same conditions
   # rlmi 6,4,5,0xFFFFFFFC
   # will produce the same result.

2. The following code rotates the contents of GPR 4 by the value contained in bits 27-31 in GPR 5, stores the masked result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:

   # Assume GPR 4 contains 0xB004 3000.
   # Assume GPR 5 contains 0x0000 0002.
   # GPR 6 is the target register and contains 0xFFFF FFFF.
   rlmi. 6,4,5,0,0x1D
   # GPR 6 now contains 0xC010 C003.
   # CRF 0 now contains 0x8.
   # Under the same conditions
   # rlmi. 6,4,5,0xFFFFFFFC
   # will produce the same result.

Related Information

Fixed-Point Processor.

Fixed-Point Rotate and Shift Instructions.