POWER and PowerPC Architecture Overview

A POWER or PowerPC microprocessor contains the sequencing and processing controls for instruction fetch, instruction execution, and interrupt action, and implements the instruction set, storage model, and other facilities defined in the POWER and PowerPC architectures.

The processor can execute three classes of instructions:

• Branch instructions
• Fixed-point instructions
• Floating-point instructions

A POWER or PowerPC microprocessor contains a branch processor, a fixed-point processor, and a floating-point processor.

The following figure is a logical representation of instruction processing for POWER and PowerPC.

The following figure shows the registers for the PowerPC user instruction set architecture.

The following figure shows the registers of the POWER user instruction set architecture.

The processing unit is a word-oriented, fixed-point processor functioning in tandem with a doubleword-oriented, floating-point processor. The microprocessor uses 32-bit word-aligned instructions. It provides for byte, halfword, and word operand fetches and stores for fixed point, and word and doubleword operand fetches and stores for floating point. These fetches and stores can occur between main storage and a set of 32 general-purpose registers, and between main storage and a set of 32 floating-point registers.

Instruction Forms

All instructions are four bytes long and are word-aligned. Therefore, when the processor fetches instructions (for example, branch instructions), the two low-order bits are ignored. Similarly, when the processor develops an instruction address, the two low-order bits of the address are 0.

Bits 0-5 always specify the op code. Many instructions also have an extended op code (for example, XO-form instructions). The remaining bits of the instruction contain one or more fields. The alternative fields for the various instruction forms are shown in the following figures:

• I Form
• B Form
• SC Form
• D Form
• DS Form
• X Instruction Format

• XL Instruction Format
• XFX Instruction Format
• XFL Instruction Format
• XO Instruction Format

For some instructions, an instruction field is reserved or must contain a particular value. This is not indicated in the previous figures, but is shown in the syntax for instructions in which these conditions are required. If a reserved field does not have all bits set to 0, or if a field that must contain a particular value does not contain that value, the instruction form is invalid. See "Detection of New Error Conditions" for more information on invalid instruction forms.

Split-Field Notation

In some cases an instruction field occupies more than one contiguous sequence of bits, or occupies a contiguous sequence of bits that are used in permuted order. Such a field is called a split field. In the previous figures and in the syntax for individual instructions, the name of a split field is shown in lowercase letters, once for each of the contiguous bit sequences. In the description of an instruction with a split field, and in certain other places where the individual bits of a split field are identified, the name of the field in lowercase letters represents the concatenation of the sequences from left to right. In all other cases, the name of the field is capitalized and represents the concatenation of the sequences in some order, which does not have to be left to right. The order is described for each affected instruction.

Instruction Fields

Let mstart=MB and mstop=ME:
If mstart < mstop + 1 then
          mask(mstart..mstop) = ones
          mask(all other) = zeros
If mstart = mstop + 1 then
          mask(0:31) = ones
If mstart > mstop + 1 then
          mask(mstop+1..mstart-1) = zeros
          mask(all other) = ones

Related Information

Processing and Storage: Overview.

Branch Processor.

Fixed-Point Processor.

Floating-Point Processor.

PowerPC Architecture.