Copies the contents of a floating-point register into the Floating-Point Status and Control Register under the control of a field mask.
mtfsf | FLM,FRB |
mtfsf. | FLM,FRB |
See "Extended Mnemonics of Condition Register Logical Instructions" for more information.
The mtfsf instruction copies bits 32-63 of the contents of the floating-point register (FPR) FRB into the Floating-Point Status and Control Register under the control of the field mask specified by FLM.
The field mask FLM is defined as follows:
Bit Description
7 FPSCR 00-03 is updated with the contents of FRB 32-35.
8 FPSCR 04-07 is updated with the contents of FRB 36-39.
9 FPSCR 08-11 is updated with the contents of FRB 40-43.
10 FPSCR 12-15 is updated with the contents of FRB 44-47.
11 FPSCR 16-19 is updated with the contents of FRB 48-51.
12 FPSCR 20-23 is updated with the contents of FRB 52-55.
13 FPSCR 24-27 is updated with the contents of FRB 56-59.
14 FPSCR 28-31 is updated with the contents of FRB 60-63.
The mtfsf instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
Syntax Form | FPSCR Bits | Record Bit (Rc) | Condition Register Field 1 |
mtfsf | None | 0 | None |
mtfsf. | None | 1 | FX, FEX, VX, OX |
The two syntax forms of the mtfsf instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Floating-Point Exception (FX), Floating-Point Enabled Exception (FEX), Floating Invalid Operation Exception (VX), and Floating-Point Overflow Exception (OX) bits in Condition Register Field 1.
Note: When specifying FPSCR 0-3, some bits cannot be explicitly set or reset.
FLM | Specifies field mask. |
FRB | Specifies source floating-point register for operation. |
# Assume bits 32-63 of FPR 5 # contain 0x3000 3000. mtfsf 0x80,5 # Floating-Point Status and Control Register # Field 0 is set to b'0001'.
# Assume bits 32-63 of FPR 5 # contains 0x2320 0000. mtfsf. 0xE0,5 # Floating-Point Status and Control Register Fields 0-2 # now contain b'0010 0011 0010'. # Condition Register Field 1 now contains 0x2.
Interpreting the Contents of a Floating-Point Register.