Stores the contents of consecutive registers into a specified memory location.
| Bits | Value |
|---|---|
| 0-5 | 47 |
| 6-10 | RT |
| 11-15 | RA |
| 16-31 | D |
| PowerPC | |
|---|---|
| stmw | RS, D( RA) |
| POWER family | |
|---|---|
| stm | RS, D( RA) |
The stmw and stm instructions store N consecutive words from general-purpose register (GPR) RS through GPR 31. Storage starts at the effective address (EA). N is a register number equal to 32 minus RS.
If GPR RA is not 0, the EA is the sum of the contents of GPR RA and D. The sum is a 16-bit signed two's complement integer sign-extended to 32 bits. If GPR RA is 0, then the EA is D.
The stmw instruction has one syntax form. If the EA is not a multiple of 4, the results are boundedly undefined.
The stm instruction has one syntax form and does not affect the Fixed-Point Exception Register or Condition Register Field 0.
The following code stores the contents of GPR 29 through GPR 31 into a location in memory:
.csect data[rw] buffer: .long 0,0,0 # Assume GPR 29 contains 0x1000 2200. # Assume GPR 30 contains 0x1000 3300. # Assume GPR 31 contains 0x1000 4400. .csect text[pr] stmw 29,buffer(4) # Three consecutive words in storage beginning at the address # of buffer are now 0x1000 2200 1000 3300 1000 4400.
Fixed-Point Load and Store Instructions .