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Assembler Language Reference

rlmi (Rotate Left Then Mask Insert) Instruction

Purpose

Rotates the contents of a general-purpose register to the left by the number of bits specified in another general-purpose register and stores the result in a third general-purpose register under the control of a generated mask.

Note: The rlmi instruction is supported only in the POWER family architecture.

Syntax

Bits Value
0-5 22
6-10 RS
11-15 RA
16-20 RB
21-25 MB
26-30 ME
31 Rc
POWER family 
rlmi RA, RS, RB, MB, ME
rlmi. RA, RS, RB, MB, ME
rlmi RA, RS, RB, BM
rlmi. RA, RS, RB, BM

See Extended Mnemonics of Fixed-Point Rotate and Shift Instructions for more information.

Description

The rlmi instruction rotates the contents of the source general-purpose register (GPR) RS to the left by the number of bits specified by bits 27-31 of GPR RB and then stores the rotated data in GPR RA under control of a 32-bit generated mask defined by the values in Mask Begin (MB) and Mask End (ME).

Consider the following when using the rlmi instruction:

The parameter BM can also be used to specify the mask for this instruction. The assembler will generate the MB and ME parameters from BM.

The rlmi instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form Overflow Exception (OE) Fixed-Point Exception Register Record Bit (Rc) Condition Register Field 0
rlmi None None 0 None
rlmi. None None 1 LT,GT,EQ,SO

The two syntax forms of the rlmi instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA Specifies target general-purpose register where result of operation is stored.
RS Specifies source general-purpose register for operation.
RB Specifies general-purpose register that contains number of bits for rotation of data.
MB Specifies begin value of mask for operation.
ME Specifies end value of mask for operation.
BM Specifies value of 32-bit mask.

Examples

  1. The following code rotates the contents of GPR 4 by the value contained in bits 27-31 in GPR 5 and stores the masked result in GPR 6:

    # Assume GPR 4 contains 0x9000 3000.
    # Assume GPR 5 contains 0x0000 0002.
    # Assume GPR 6 contains 0xFFFF FFFF.
    rlmi 6,4,5,0,0x1D
    # GPR 6 now contains 0x4000 C003.
    # Under the same conditions
    # rlmi 6,4,5,0xFFFFFFFC
    # will produce the same result.
  2. The following code rotates the contents of GPR 4 by the value contained in bits 27-31 in GPR 5, stores the masked result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:

    # Assume GPR 4 contains 0xB004 3000.
    # Assume GPR 5 contains 0x0000 0002.
    # GPR 6 is the target register and contains 0xFFFF FFFF.
    rlmi. 6,4,5,0,0x1D
    # GPR 6 now contains 0xC010 C003.
    # CRF 0 now contains 0x8.
    # Under the same conditions
    # rlmi. 6,4,5,0xFFFFFFFC
    # will produce the same result.

Related Information

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .

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