This section discusses the following:
The following instructions are available in POWER family and PowerPC. These instructions share the same op code and mnemonic, and have the same function in POWER family and PowerPC, but use different input operand formats.
The input operand format for POWER family is:
BF, RA, SI | RB | UI
The input operand format for PowerPC is:
BF, L, RA, SI | RB | UI
The assembler handles these as the same instructions in POWER family and PowerPC, but with different input operand formats. The L operand is one bit. For POWER family, the assembler presets this bit to 0. For 32-bit PowerPC platforms, this bit must be set to 0, or an invalid instruction form results.
The instructions listed in the following table are available in POWER family and PowerPC. These instructions share the same op code and function, but have different mnemonics and input operand formats. The assembler still places them in the POWER family/PowerPC intersection area, because the same binary code is generated. If the -s option is used, no cross-reference is given, because it is necessary to change the source code when migrating from POWER family to PowerPC, or vice versa.
POWER family | PowerPC |
---|---|
cal | addi |
mtsri | mtsrin |
svca | sc |
cau | addis |
To maintain source compatibility of the cau and addis instructions, the assembler expands the value range check to (-65536, 65535) for the addis instruction. The sign bit is ignored and the assembler ensures only that the immediate value fits in 16 bits. This expansion does not affect the behavior of a 32-bit implementation.
For a 64-bit implementation, if bit 32 is set, it is propagated through the upper 32 bits of the 64-bit general-purpose register (GPR). Therefore, if an immediate value within the range (32768, 65535) or (-65536, -32767) is used for the addis instruction in a 32-bit mode, this immediate value may not be directly ported to a 64-bit mode.
Moving from the DEC (decrement) special purpose register is privileged in PowerPC, but nonprivileged in POWER family. One bit in the instruction field that specifies the register is 1 for privileged operations, but 0 for nonprivileged operations. As a result, the encoding number for the DEC SPR for the mfdec instruction has different values in PowerPC and POWER family. The DEC encoding number is 22 for PowerPC and 6 for POWER family. If the mfdec instruction is used, the assembler determines the DEC encoding based on the current assembly mode. The following list shows the assembler processing of the mfdec instruction for each assembly mode value:
Functional Differences for POWER family and PowerPC Instructions.
POWER family Instructions Deleted from PowerPC.
Instructions Available Only for the PowerPC 601 RISC Microprocessor.