Multiply 2 64-bit values together. Place the low-order 64 bits of the result into a register.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | D |
| 11-15 | A |
| 16-20 | B |
| 21 | OE |
| 22-30 | 233 |
| 31 | Rc |
| POWER family | |
|---|---|
| mulld | RT, RA, RB (OE=0 Rc=0) |
| mulld. | RT, RA, RB (OE=0 Rc=1) |
| mulldo | RT, RA, RB (OE=1 Rc=0) |
| mulldo. | RT, RA, RB (OE=1 Rc=1) |
The 64-bit operands are the contents of general purpose registers (GPR) RA and RB. The low-order 64 bits of the 128-bit product of the operands are placed into RT.
Both the operands and the product are interpreted as signed integers. The low-order 64 bits of the product are independent of whether the operands are regarded as signed or unsigned 64-bit integers. If OE = 1 (the mulldo and mulldo. instructions), then OV is set if the product cannot be represented in 64 bits.
This instruction may execute faster on some implementations if RB contains the operand having the smaller absolute value.
Other registers altered:
Affected: LT, GT, EQ, SO (if Rc = 1)
Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).
Affected: SO, OV (if OE = 1)
Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit result.
This instruction is defined only for 64-bit implementations. Using it on a 32-bit implementation will cause the system illegal instruction error handler to be invoked.