Assembler Language Reference

mulhwu (Multiply High Word Unsigned) Instruction

Purpose

Computes the most significant 32 bits of the 64-bit product of two unsigned 32-bit integers.

Note: The mulhwu instruction is supported only in the PowerPC architecture.

Syntax

Bits	Value
0-5	31
6-10	RT
11-15	RA
16-20	RB
21	/
22-30	11
31	Rc

PowerPC
mulhwu	RT, RA, RB
mulhwu.	RT, RA, RB

Description

The mulhwu instruction multiplies the contents of general-purpose register (GPR) RA and GPR RB and places the most significant 32 bits of the 64-bit product in the target GPR RT. Both the operands and the product are interpreted as unsigned integers.

Note: Although the operation treats the result as an unsigned integer, the setting of the Condition Register Field 0 for the Less Than (LT) zero, Greater Than (GT) zero, and Equal To (EQ) zero bits are interpreted as signed integers.

The mulhwu instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Record Bit (Rc)	Condition Register Field 0
mulhwu	0	None
mulhwu.	1	LT,GT,EQ,SO

If the syntax form sets the Record (Rc) bit to 1, then the Less Than (LT) zero, Greater Than (GT) zero and Equal To (EQ) zero bits in Condition Register Field 0 reflect the result placed in GPR RT, and the Summary Overflow (SO) bit is copied from the XER to the SO bit in Condition Register Field 0.

Parameters

RT	Specifies target general-purpose register where result of operation is stored.
RA	Specifies source general-purpose register for EA calculation.
RB	Specifies source general-purpose register for EA calculation.

Examples

The following code multiplies the contents of GPR 4 by the contents of GPR 10 and stores the result in GPR 6:

# Assume GPR 4 contains 0x0000 0003.
# Assume GPR 10 contains 0x0000 0002.
mulhwu 6,4,10
# GPR 6 now contains 0x0000 0000.

The following code multiplies the contents of GPR 4 by the contents of GPR 10, stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:

# Assume GPR 4 contains 0x0000 4500.
# Assume GPR 10 contains 0x8000 7000.
# Assume XER(SO) = 0.
mulhwu. 6,4,10
# GPR 6 now contains 0x0000 2280.
# Condition Register Field 0 now contains 0x4.

Related Information

The mul (Multiply) instruction, mulhw (Multiply High Word) instruction, mulli or muli (Multiply Low Immediate) instruction, mullw or muls (Multiply Low Word) instruction.

Fixed-Point Processor .

Fixed-Point Arithmetic Instructions .