Copies the contents of a calculated segment register into a general-purpose register.
Note: The mfsri instruction is supported only in the POWER family architecture.
| Bits | Value |
|---|---|
| 0-5 | 31 |
| 6-10 | RS |
| 11-15 | RA |
| 16-20 | RB |
| 21-30 | 627 |
| 31 | Rc |
| POWER family | |
|---|---|
| mfsri | RS, RA, RB |
The mfsri instruction copies the contents of segment register (SR), specified by bits 0-3 of the calculated contents of the general-purpose register (GPR) RA, into GPR RS. If RA is not 0, the specifying bits in GPR RA are calculated by adding the original contents of RA to GPR RB and placing the sum in RA. If RA = RS, the sum is not placed in RA.
The mfsri instruction has one syntax form and does not affect the Fixed-Point Exception Register. If the Record (Rc) bit is set to 1, Condition Register Field 0 is undefined.
The following code copies the contents of the segment register specified by the first 4 bits of the sum of the contents of GPR 4 and GPR 5 into GPR 6:
# Assume that GPR 4 contains 0x9000 3000. # Assume that GPR 5 contains 0x1000 0000. # Assume that GPR 6 is the target register. mfsri 6,5,4 # GPR 6 now contains the contents of Segment Register 10.
The mfsrin (Move from Segment Register Indirect) instruction, mtsr (Move to Segment Register) instruction, mtsrin or mtsri (Move to Segment Register Indirect) instruction.