Assembler Language Reference

maskir (Mask Insert from Register) Instruction

Purpose

Inserts the contents of one general-purpose register into another general-purpose register under control of a bit mask.

Note: The maskir instruction is supported only in the POWER family architecture.

Syntax

Bits	Value
0-5	31
6-10	RS
11-15	RA
16-20	RB
21-30	541
31	Rc

POWER family
maskir	RA, RS, RB
maskir.	RA, RS, RB

Description

The maskir stores the contents of general-purpose register (GPR) RS in GPR RA under control of the bit mask in GPR RB.

The value for each bit in the target GPR RA is determined as follows:

If the corresponding bit in the mask GPR RB is 1, then the bit in the target GPR RA is given the value of the corresponding bit in the source GPR RS.

If the corresponding bit in the mask GPR RB is 0, then the bit in the target GPR RA is unchanged.

The maskir instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
maskir	None	None	0	None
maskir.	None	None	1	LT, GT, EQ, SO

The two syntax forms of the maskir instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA	Specifies target general-purpose register where result of operation is stored.
RS	Specifies source general-purpose register for operation.
RB	Specifies source general-purpose register for bit mask.

Examples

The following code inserts the contents of GPR 5 into GPR 6 under control of the bit mask in GPR 4:

# Assume GPR 6 (RA) target contains 0xAAAAAAAA.
# Assume GPR 4 (RB) mask contains   0x000F0F00.
# Assume GPR 5 (RS) source contains 0x55555555.
maskir 6,5,4
# GPR 6 (RA) target now contains    0xAAA5A5AA.

The following code inserts the contents of GPR 5 into GPR 6 under control of the bit mask in GPR 4 and sets Condition Register Field 0 to reflect the result of the operation:

# Assume GPR 6 (RA) target contains 0xAAAAAAAA.
# Assume GPR 4 (RB) mask contains   0x0A050F00.
# Assume GPR 5 (RS) source contains 0x55555555.
maskir. 6,5,4
# GPR 6 (RA) target now contains    0xA0AFA5AA.

Related Information

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .