Assembler Language Reference

maskg (Mask Generate) Instruction

Purpose

Generates a mask of ones and zeros and loads it into a general-purpose register.

Note: The maskg instruction is supported only in the POWER family architecture.

Syntax

Bits	Value
0-5	31
6-10	RS
11-15	RA
16-20	RB
21-30	29
31	Rc

POWER family
maskg	RA, RS, RB
maskg.	RA, RS, RB

Description

The maskg instruction generates a mask from a starting point defined by bits 27-31 of general-purpose register (GPR) RS to an end point defined by bits 27-31 of GPR RB and stores the mask in GPR RA.

Consider the following when using the maskg instruction:

If the starting point bit is less than the end point bit + 1, then the bits between and including the starting point and the end point are set to ones. All other bits are set to 0.

If the starting point bit is the same as the end point bit + 1, then all 32 bits are set to ones.

If the starting point bit is greater than the end point bit + 1, then all of the bits between and including the end point bit + 1 and the starting point bit - 1 are set to zeros. All other bits are set to ones.

The maskg instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

Syntax Form	Overflow Exception (OE)	Fixed-Point Exception Register	Record Bit (Rc)	Condition Register Field 0
maskg	None	None	0	None
maskg.	None	None	1	LT,GT,EQ,SO

The two syntax forms of the maskg instruction never affect the Fixed-Point Exception Register. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0.

Parameters

RA	Specifies target general-purpose register where result of operation is stored.
RS	Specifies source general-purpose register for start of mask.
RB	Specifies source general-purpose register for end of mask.

Examples

The following code generates a mask of 5 ones and stores the result in GPR 6:

# Assume GPR 4 contains 0x0000 0014.
# Assume GPR 5 contains 0x0000 0010.
maskg 6,5,4
# GPR 6 now contains 0x0000 F800.

The following code generates a mask of 6 zeros with the remaining bits set to one, stores the result in GPR 6, and sets Condition Register Field 0 to reflect the result of the operation:
```
# Assume GPR 4 contains 0x0000 0010.
# Assume GPR 5 contains 0x0000 0017.
# Assume CR = 0.
maskg. 6,5,4
# GPR 6 now contains 0xFFFF 81FF.
# CR now contains 0x8000 0000.
```

Related Information

Fixed-Point Processor .

Fixed-Point Rotate and Shift Instructions .