Assembler Language Reference

lscbx (Load String and Compare Byte Indexed) Instruction

Purpose

Loads consecutive bytes in storage into consecutive registers.

Note: The lscbx instruction is supported only in the POWER family architecture.

Syntax

Description

The lscbx instruction loads N consecutive bytes addressed by effective address (EA) into general-purpose register (GPR) RT, starting with the leftmost byte in register RT, through RT + NR - 1, and wrapping around back through GPR 0, if required, until either a byte match is found with XER16-23 or N bytes have been loaded. If a byte match is found, then that byte is also loaded.

If GPR RA is not 0, the EA is the sum of the contents of GPR RA and the address stored in GPR RB. If RA is 0, then EA is the contents of GPR RB.

Consider the following when using the lscbx instruction:

• XER(16-23) contains the byte to be compared.
• XER(25-31) contains the byte count before the instruction is invoked and the number of bytes loaded after the instruction has completed.
• If XER(25-31) = 0, GPR RT is not altered.
• N is XER(25-31), which is the number of bytes to load.
• NR is ceiling(N/4), which is the total number of registers required to contain the consecutive bytes.

Bytes are always loaded left to right in the register. In the case when a match was found before N bytes were loaded, the contents of the rightmost bytes not loaded from that register and the contents of all succeeding registers up to and including register RT + NR - 1 are undefined. Also, no reference is made to storage after the matched byte is found. In the case when a match was not found, the contents of the rightmost bytes not loaded from register RT + NR - 1 are undefined.

If GPR RA is not 0 and GPRs RA and RB are in the range to be loaded, then GPRs RA and RB are not written to. The data that would have been written into them is discarded, and the operation continues normally. If the byte in XER(16-23) compares with any of the 4 bytes that would have been loaded into GPR RA or RB, but are being discarded for restartability, the EQ bit in the Condition Register and the count returned in XER(25-31) are undefined. The Multiply Quotient (MQ) Register is not affected by this operation.

The lscbx instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 0.

The two syntax forms of the lscbx instruction place the number of bytes loaded into Fixed-Point Exception Register (XER) bits 25-31. If the syntax form sets the Record (Rc) bit to 1, the instruction affects the Less Than (LT) zero, Greater Than (GT) zero, Equal To (EQ) zero, and Summary Overflow (SO) bits in Condition Register Field 0. If Rc = 1 and XER(25-31) = 0, then Condition Register Field 0 is undefined. If Rc = 1 and XER(25-31) <> 0, then Condition Register Field 0 is set as follows:

LT, GT, EQ, SO = b'00'||match||XER(SO)

Note: This instruction can be interrupted by a Data Storage interrupt. When such an interrupt occurs, the instruction is restarted from the beginning.

Parameters

Examples

1. The following code loads consecutive bytes into GPRs 6, 7, and 8:

   .csect data[rw]
   string: "Hello, world"
   # Assume XER16-23 = 'a.
   # Assume XER25-31 = 9.
   # Assume GPR 5 contains the address of csect data[rw].
   # Assume GPR 4 contains the displacement of string relative
   # to csect data[rw].
   .csect text[pr]
   lscbx 6,5,4
   # GPR 6 now contains 0x4865 6c6c.
   # GPR 7 now contains 0x6f2c 2077.
   # GPR 8 now contains 0x6fXX XXXX.

2. The following code loads consecutive bytes into GPRs 6, 7, and 8:

   # Assume XER16-23 = 'e.
   # Assume XER25-31 = 9.
   # Assume GPR 5 contains the address of csect data[rw].
   # Assume GPR 4 contains the displacement of string relative
   # to csect data[rw].
   .csect text[pr]
   lscbx. 6,5,4
   # GPR 6 now contains 0x4865 XXXX.
   # GPR 7 now contains 0xXXXX XXXX.
   # GPR 8 now contains 0xXXXX XXXX.
   # XER25-31 = 2.
   # CRF 0 now contains 0x2.

Related Information

Fixed-Point Processor .

Fixed-Point String Instructions .