Assembler Language Reference

lfsux (Load Floating-Point Single with Update Indexed) Instruction

Purpose

Loads a floating-point, single-precision number that has been converted to a floating-point, double-precision number into a floating-point register and possibly places the effective address in a general-purpose register.

Syntax

Bits	Value
0-5	31
6-10	FRT
11-15	RA
16-20	RB
21-30	567
31	/

lfsux

FRT, RA, RB

Description

The lfsux instruction converts a floating-point, single-precision word in storage addressed by the effective address (EA) to floating-point, double-precision word and loads the result into floating-point register (FPR) FRT.

If general-purpose register (GPR) RA is not 0, the EA is the sum of the contents of GPR RA and GPR RB. If RA is 0, then the EA is the contents of GPR RB.

If GPR RA does not equal 0 and the storage access does not cause an Alignment interrupt or a Data Storage interrupt, then the EA is stored in GPR RA.

The lfsux instruction has one syntax form and does not affect the Floating-Point Status Control Register.

Parameters

FRT	Specifies target floating-point register where data is stored.
RA	Specifies source general-purpose register for EA calculation and possible address update.
RB	Specifies source general-purpose register for EA calculation.

Examples

The following code loads the single-precision contents of storage into FPR 6 and stores the effective address in GPR 5:

.csect data[rw]
storage: .float 0x1
# Assume GPR 4 contains the address of csect data[rw].
# Assume GPR 5 contains the displacement of storage
# relative to .csect data[rw].
.csect text[pr]
lfsux 6,5,4
# FPR 6 now contains 0x3FF0 0000 0000 0000.
# GPR 5 now contains the storage address.

Related Information

Floating-Point Processor .

Floating-Point Load and Store Instructions .