Loads a floating-point, single-precision number that has been converted to a floating-point, double-precision number into a floating-point register and possibly places the effective address in a general-purpose register.
| Bits | Value |
|---|---|
| 0-5 | 49 |
| 6-10 | FRT |
| 11-15 | RA |
| 16-31 | D |
| lfsu | FRT, D( RA) |
The lfsu instruction converts a floating-point, single-precision word in storage addressed by the effective address (EA) to floating-point, double-precision word and loads the result into floating-point register (FPR) FRT.
If RA is not 0, the EA is the sum of the contents of general-purpose register (GPR) RA and D, a 16-bit signed two's complement integer sign extended to 32 bits. If RA is 0, then the EA is D.
If RA does not equal 0 and the storage access does not cause an Alignment interrupt or a Data Storage interrupt, then the EA is stored in GPR RA.
The lfsu instruction has one syntax form and does not affect the Floating-Point Status and Control Register or Condition Register Field 0.
The following code loads the single-precision contents of storage, which is converted to double precision, into FPR 6 and stores the effective address in GPR 5:
.csect data[rw] storage: .float 0x1 .csect text[pr] # Assume GPR 5 contains the storage address. lfsu 6,0(5) # FPR 6 now contains 0x3FF0 0000 0000 0000. # GPR 5 now contains the storage address.
Floating-Point Load and Store Instructions .