Calculate the square root of the contents of a floating- point register, placing the result in a floating-point register.
| Bits | Value |
|---|---|
| 0-5 | 63 |
| 6-10 | D |
| 11-15 | 00000 |
| 16-20 | B |
| 21-25 | 00000 |
| 26-30 | 22 |
| 31 | Rc |
| PowerPC | |
|---|---|
| fsqrt | FRT, FRB (Rc=0) |
| fsqrt. | FRT, FRB (Rc=1) |
The square root of the operand in floating-point register (FPR) FRB is placed into register FPR FRT.
If the most-significant bit of the resultant significand is not a one the result is normalized. The result is rounded to the target precision under control of the floating-point rounding control field RN of the FPSCR and placed into register FPR FRT.
Operation with various special values of the operand is summarized below.
| Operand | Result | Exception |
|---|---|---|
| - infinity | QNaN* | VXSQRT |
| < 0 | QNaN* | VXSQRT |
| - 0 | - 0 | None |
| + infinity | + infinity | None |
| SNaN | QNaN* | VXSNAN |
| QNaN | QNaN | None |
Notes: * No result if FPSCR[VE] = 1
FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = 1.
The fsqrt instruction has two syntax forms. Each syntax form has a different effect on Condition Register Field 1.
| Syntax Form | Floating-Point Status and Control Register | Record Bit (Rc) | Condition Register Field 1 |
| fsqrt | FPRF,FR,FI,FX,XX,VXSNAN,VXSQRT | 0 | None |
| fsqrt. | FPRF,FR,FI,FX,XX,VXSNAN,VXSQRT | 1 | FX,FEX,VX,OX |
| FRT | Specifies the target floating-point register for the operation. |
| FRB | Specifies the source floating-point register for the operation. |
This instruction is optionally defined for PowerPC implementations. Using it on an implementation that does not support this instruction will cause the system illegal instruction error handler to be invoked.
This instruction is an optional instruction of the PowerPC architecture and may not be implemented in all machines.